diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/dm1105/dm1105.c kernel-2.6.24.4-twinhan/drivers/media/dvb/dm1105/dm1105.c --- kernel-2.6.24.4-orig/drivers/media/dvb/dm1105/dm1105.c 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/dm1105/dm1105.c 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,648 @@ +/* + * dm1105.c - DVBWorld PCI2002 [DVB-S] + * + * Copyright (C) 2007 Igor M. Liplianin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include +#include +#include +#include + +#include "demux.h" +#include "dmxdev.h" +#include "dvb_demux.h" +#include "dvb_frontend.h" +#include "dvb_net.h" +#include "dvbdev.h" +#include "dvb-pll.h" +#include "stv0299.h" +#include "bsru6.h" + +/* sdmc dm1105 registers */ +/* ----------------------------------------------- */ +/* + * PCI ID's + */ +#ifndef PCI_DEVICE_ID_TRIGEM_DM1105 +# define PCI_DEVICE_ID_TRIGEM_DM1105 0x036f +#endif +/* ----------------------------------------------- */ + +/* TS Control */ +#define DM1105_TSCTR 0x00 +#define DM1105_DTALENTH 0x04 + +/* GPIO Interface */ +#define DM1105_GPIOVAL 0x08 +#define DM1105_POWER 0x08 +#define GPIO89DATA 0x09 +#define DM1105_GPIOCTR 0x0c +#define GPIO89DIR 0x0d + +/* PID serial number */ +#define DM1105_PIDN 0x10 + +/* Odd-even secret key select */ +#define DM1105_CWSEL 0x14 + +/* Host Command Interface */ +#define DM1105_HOST_CTR 0x18 +#define DM1105_HOST_AD 0x1c + +/* PCI Interface */ +#define DM1105_CR 0x30 +#define DM1105_RST 0x34 +#define DM1105_STADR 0x38 +#define DM1105_RLEN 0x3c +#define DM1105_WRP 0x40 +#define DM1105_INTCNT 0x44 +#define DM1105_INTMAK 0x48 +#define DM1105_INTSTS 0x4c + +/* CW Value */ +#define DM1105_ODD 0x50 +#define DM1105_EVEN 0x58 + +/* PID Value */ +#define DM1105_PID 0x60 + +/* IR Control */ +#define DM1105_IRCTR 0x64 +#define DM1105_IRMODE 0x68 +#define DM1105_SYSTEMCODE 0x6c +#define DM1105_IRCODE 0x70 + +/* I2C Interface */ +#define DM1105_I2CCTR 0x80 +#define DM1105_I2CSTS 0x81 +#define DM1105_I2CDAT 0x82 +#define DM1105_I2C_RA 0x83 + +/* Masks */ +#define INTMAK_ALLMASK 0x01 + +/* EEPROM addr */ +#define IIC_24C01_addr 0xa0 +/* Max board count */ +#define DM1105_MAX 0x04 +/* ----------------------------------------------- */ + +#define DRIVER_NAME "dm1105" + +#define DM1105_DMA_PACKETS (47) +#define DM1105_DMA_BYTES (128 * 4 * DM1105_DMA_PACKETS) + +#ifndef PCI_VENDOR_ID_TRIGEM +#define PCI_VENDOR_ID_TRIGEM 0x109f +#endif +#ifndef PCI_VENDOR_ID_AXESS +#define PCI_VENDOR_ID_AXESS 0x195d +#endif + +#ifndef PCI_DEVICE_ID_DM1105 +#define PCI_DEVICE_ID_DM1105 0x036f +#endif +#ifndef PCI_DEVICE_ID_DM1105S +#define PCI_DEVICE_ID_DM1105S 0x1105 +#endif + +struct dm1105dvb { + /* pci */ + struct pci_dev *pdev; + u8 __iomem *io_mem; + + /* dvb */ + struct dmx_frontend hw_frontend; + struct dmx_frontend mem_frontend; + struct dmxdev dmxdev; + struct dvb_adapter dvb_adapter; + struct dvb_demux demux; + struct dvb_frontend *fe; + struct dvb_net dvbnet; + unsigned int full_ts_users; + + /* i2c */ + struct i2c_adapter i2c_adap; + + /* dma */ + dma_addr_t dma_addr; + unsigned char *ts_buf; + u32 wrp; + u32 buffer_size; + unsigned int PacketErrorCount; + unsigned int dmarst; + spinlock_t lock; + +}; + +static int dm1105_i2c_xfer(struct i2c_adapter *i2c_adap, + struct i2c_msg *msgs, int num) +{ + struct dm1105dvb *dm1105dvb ; + + int addr,rc,i,j,byte,data; + void *ioaddr; + u8 status; + + dm1105dvb = i2c_adap->algo_data; + ioaddr = dm1105dvb->io_mem; + for (i = 0; i < num; i++) { + outb(0x00, (unsigned long)(&dm1105dvb->io_mem[DM1105_I2CCTR])); + if (msgs[i].flags & I2C_M_RD) { + /* read bytes */ + addr = msgs[i].addr << 1; + addr |= 1; + outb(addr, (unsigned long)(&dm1105dvb->io_mem[DM1105_I2CDAT])); + for (byte = 0; byte < msgs[i].len; byte++) { + outb(0, (unsigned long)(&dm1105dvb->io_mem[DM1105_I2CDAT+byte+1])); + } + outb(0x81 + msgs[i].len, (unsigned long)(&dm1105dvb->io_mem[DM1105_I2CCTR])); + for (j = 0; j < 55; i++){ + mdelay (10); // 10ms + status = inb((unsigned long)&dm1105dvb->io_mem[DM1105_I2CSTS]); + if ((status & 0xc0) == 0x40) + break; + } + if (j >= 55){ + return -1; + } + for (byte = 0; byte < msgs[i].len; byte++) { + + rc = inb((unsigned long)(&dm1105dvb->io_mem[DM1105_I2CDAT+byte+1])); + if (rc < 0) + goto err; + msgs[i].buf[byte] = rc; + + } + } else { + /* write bytes */ + outb(msgs[i].addr<<1, (unsigned long)(&dm1105dvb->io_mem[DM1105_I2CDAT])); + for (byte = 0; byte < msgs[i].len; byte++) { + data = msgs[i].buf[byte]; + outb(data, (unsigned long)(&dm1105dvb->io_mem[DM1105_I2CDAT+byte+1])); + } + outb(0x81 + msgs[i].len, (unsigned long)(&dm1105dvb->io_mem[DM1105_I2CCTR])); + for (j = 0; j < 25; i++){ + mdelay (10); // 10ms + status = inb((unsigned long)(&dm1105dvb->io_mem[DM1105_I2CSTS])); + if ((status & 0xc0) == 0x40) + break; + } + + if (j >= 25){ + return -1; + } + } + } + return num; + err: + return rc; +} + +static u32 functionality(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C; +} + +static struct i2c_algorithm dm1105_algo = { + .master_xfer = dm1105_i2c_xfer, + .functionality = functionality, +}; + +static inline struct dm1105dvb *feed_to_dm1105dvb(struct dvb_demux_feed *feed) +{ + return container_of(feed->demux, struct dm1105dvb, demux); +} + +static inline struct dm1105dvb *frontend_to_dm1105dvb(struct dvb_frontend *fe) +{ + return container_of(fe->dvb, struct dm1105dvb, dvb_adapter); +} + +static int dm1105dvb_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) +{ + struct dm1105dvb *dm1105dvb = frontend_to_dm1105dvb(fe); + + if (voltage == SEC_VOLTAGE_18) { + outl(0xFFFcFFFF, (unsigned long)(&dm1105dvb->io_mem[DM1105_GPIOCTR])); + outl(0xFF1FF, (unsigned long)(&dm1105dvb->io_mem[DM1105_POWER])); + }else { + /*LNB ON-13V by default!*/ + outl(0xFFF1FFFF, (unsigned long)(&dm1105dvb->io_mem[DM1105_GPIOCTR])); + outl(0xFF1FF, (unsigned long)(&dm1105dvb->io_mem[DM1105_POWER])); + } + + return 0; +} + +static void dm1105dvb_set_dma_addr(struct dm1105dvb *dm1105dvb) +{ + outl(cpu_to_le32(dm1105dvb->dma_addr), (unsigned long)(&dm1105dvb->io_mem[DM1105_STADR])); +} + +static int __devinit dm1105dvb_dma_map(struct dm1105dvb *dm1105dvb) +{ + dm1105dvb->ts_buf = pci_alloc_consistent(dm1105dvb->pdev, 6*DM1105_DMA_BYTES, &dm1105dvb->dma_addr); + + return pci_dma_mapping_error(dm1105dvb->dma_addr); +} + +static void dm1105dvb_dma_unmap(struct dm1105dvb *dm1105dvb) +{ + pci_free_consistent(dm1105dvb->pdev, 6*DM1105_DMA_BYTES, dm1105dvb->ts_buf, dm1105dvb->dma_addr); +} + +static void __devinit dm1105dvb_enable_irqs(struct dm1105dvb *dm1105dvb) +{ + outb(1, (unsigned long)(&dm1105dvb->io_mem[DM1105_INTMAK])); + outb(1, (unsigned long)(&dm1105dvb->io_mem[DM1105_CR])); +} + +static void dm1105dvb_disable_irqs(struct dm1105dvb *dm1105dvb) +{ + outb(0, (unsigned long)(&dm1105dvb->io_mem[DM1105_INTMAK])); + outb(0, (unsigned long)(&dm1105dvb->io_mem[DM1105_CR])); +} + +static int dm1105dvb_start_feed(struct dvb_demux_feed *f) +{ + struct dm1105dvb *dm1105dvb = feed_to_dm1105dvb(f); + + if (dm1105dvb->full_ts_users++ == 0){ + dm1105dvb_enable_irqs(dm1105dvb); + } + return 0; +} + +static int dm1105dvb_stop_feed(struct dvb_demux_feed *f) +{ + struct dm1105dvb *dm1105dvb = feed_to_dm1105dvb(f); + + if (--dm1105dvb->full_ts_users == 0){ + dm1105dvb_disable_irqs(dm1105dvb); + } + return 0; +} + +static irqreturn_t dm1105dvb_irq(int irq, void *dev_id) +{ + struct dm1105dvb *dm1105dvb = dev_id; + unsigned int piece; + unsigned int nbpackets = 0; + u32 nextwrp = inl((unsigned long)(&dm1105dvb->io_mem[DM1105_WRP])) - + inl((unsigned long)(&dm1105dvb->io_mem[DM1105_STADR])) ; + u32 oldwrp = dm1105dvb->wrp; + + if (nextwrp==oldwrp){ + return IRQ_HANDLED; + } + spin_lock(&dm1105dvb->lock); + if (!((dm1105dvb->ts_buf[oldwrp] == 0x47 ) && (dm1105dvb->ts_buf[oldwrp + 188]== 0x47 ) + && (dm1105dvb->ts_buf[oldwrp + 188*2] == 0x47))) { + dm1105dvb->PacketErrorCount++; + /*printk("Bad Packet Found! NIC Device Reset ! ----%06x ----%06x\n",oldwrp,nextwrp);*/ + if((dm1105dvb->PacketErrorCount >= 2)&&(dm1105dvb->dmarst == 0)){ + outb(1, (unsigned long)(&dm1105dvb->io_mem[DM1105_RST])); + dm1105dvb->wrp = 0; + dm1105dvb->PacketErrorCount = 0; + dm1105dvb->dmarst = 0; + spin_unlock(&dm1105dvb->lock); + return IRQ_HANDLED; + } + } + if (nextwrp < oldwrp){ + piece = dm1105dvb->buffer_size - oldwrp; + memcpy(dm1105dvb->ts_buf + dm1105dvb->buffer_size, dm1105dvb->ts_buf, nextwrp); + nbpackets = (piece + nextwrp)/188; + }else { + nbpackets = (nextwrp - oldwrp)/188; + } + if (nbpackets==128) {dvb_dmx_swfilter_packets(&dm1105dvb->demux, &dm1105dvb->ts_buf[oldwrp], nbpackets); + dm1105dvb->wrp = nextwrp; + } + spin_unlock(&dm1105dvb->lock); + return IRQ_HANDLED; +} + +static int __devinit dm1105dvb_hw_init(struct dm1105dvb *dm1105dvb) +{ + //disable_irq(dm1105dvb->pdev->irq); + dm1105dvb_disable_irqs(dm1105dvb); + + outb(0, (unsigned long)(&dm1105dvb->io_mem[DM1105_INTSTS])); + outb(0, (unsigned long)(&dm1105dvb->io_mem[DM1105_IRCTR])); + outb(0, (unsigned long)(&dm1105dvb->io_mem[DM1105_HOST_CTR])); + + /*DATALEN 188,*/ + outb(188, (unsigned long)(&dm1105dvb->io_mem[DM1105_DTALENTH])); + /*TS_STRT TS_VALP MSBFIRST TS_MODE ALPAS TSPES*/ + outw(0xc10a, (unsigned long)(&dm1105dvb->io_mem[DM1105_TSCTR])); + + /* map DMA and set address */ + dm1105dvb_dma_map(dm1105dvb); + dm1105dvb_set_dma_addr(dm1105dvb); + /* big buffer */ + outl(5*DM1105_DMA_BYTES, (unsigned long)(&dm1105dvb->io_mem[DM1105_RLEN])); + outb(47, (unsigned long)(&dm1105dvb->io_mem[DM1105_INTCNT])); + + return 0; +} + +static void dm1105dvb_hw_exit(struct dm1105dvb *dm1105dvb) +{ + dm1105dvb_disable_irqs(dm1105dvb); + dm1105dvb_dma_unmap(dm1105dvb); +} + +static int __devinit frontend_init(struct dm1105dvb *dm1105dvb) +{ + int ret; + + dm1105dvb->fe = dvb_attach( + stv0299_attach, &alps_bsru6_config, + &dm1105dvb->i2c_adap); + + if (!dm1105dvb->fe) { + dev_err(&dm1105dvb->pdev->dev, "could not attach frontend\n"); + return -ENODEV; + } + dm1105dvb->fe->ops.set_voltage = dm1105dvb_set_voltage; + + dvb_attach( + dvb_pll_attach, dm1105dvb->fe, 0x60, + &dm1105dvb->i2c_adap, DVB_PLL_OPERA1); + + + ret = dvb_register_frontend(&dm1105dvb->dvb_adapter, dm1105dvb->fe); + if (ret < 0) { + if (dm1105dvb->fe->ops.release) + dm1105dvb->fe->ops.release(dm1105dvb->fe); + dm1105dvb->fe = NULL; + return ret; + } + + return 0; +} + +static void __devinit dm1105dvb_read_mac(struct dm1105dvb *dm1105dvb, u8 *mac) +{ + static u8 command[1]={0x28}; + + struct i2c_msg msg[] = { + {.addr = IIC_24C01_addr>>1, .flags = 0, .buf = command, .len = 1}, + {.addr = IIC_24C01_addr>>1, .flags = I2C_M_RD, .buf = mac, .len = 6}, + }; + + dm1105_i2c_xfer(&dm1105dvb->i2c_adap, msg , 2); + dev_info(&dm1105dvb->pdev->dev, "MAC %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); +} + +static int __devinit dm1105_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct dm1105dvb *dm1105dvb; + struct dvb_adapter *dvb_adapter; + struct dvb_demux *dvbdemux; + struct dmx_demux *dmx; + int ret = -ENOMEM; + + dm1105dvb = kzalloc(sizeof(struct dm1105dvb), GFP_KERNEL); + if (!dm1105dvb) + goto out; + + dm1105dvb->pdev = pdev; + dm1105dvb->buffer_size = 5*DM1105_DMA_BYTES; + dm1105dvb->PacketErrorCount = 0; + dm1105dvb->dmarst = 0; + + ret = pci_enable_device(pdev); + if (ret < 0) + goto err_kfree; + + ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK); + if (ret < 0) + goto err_pci_disable_device; + + pci_set_master(pdev); + + ret = pci_request_regions(pdev, DRIVER_NAME); + if (ret < 0) + goto err_pci_disable_device; + + dm1105dvb->io_mem = pci_iomap(pdev, 0, pci_resource_len (pdev, 0)); + if (!dm1105dvb->io_mem) { + ret = -EIO; + goto err_pci_release_regions; + } + + spin_lock_init (&dm1105dvb->lock); + pci_set_drvdata(pdev, dm1105dvb); + + ret = request_irq(pdev->irq, dm1105dvb_irq, IRQF_SHARED, DRIVER_NAME, dm1105dvb); + if (ret < 0) + goto err_pci_iounmap; + + ret = dm1105dvb_hw_init(dm1105dvb); + if (ret < 0) + goto err_free_irq; + + /* i2c */ + i2c_set_adapdata(&dm1105dvb->i2c_adap, dm1105dvb); + strcpy(dm1105dvb->i2c_adap.name, DRIVER_NAME); + dm1105dvb->i2c_adap.owner = THIS_MODULE; + dm1105dvb->i2c_adap.class = I2C_CLASS_TV_DIGITAL; + dm1105dvb->i2c_adap.dev.parent = &pdev->dev; + dm1105dvb->i2c_adap.algo = &dm1105_algo; + dm1105dvb->i2c_adap.algo_data = dm1105dvb; + ret = i2c_add_adapter(&dm1105dvb->i2c_adap); + + if (ret < 0) + goto err_dm1105dvb_hw_exit; + + /* dvb */ + ret = dvb_register_adapter(&dm1105dvb->dvb_adapter, DRIVER_NAME, THIS_MODULE, &pdev->dev); + if (ret < 0) + goto err_i2c_del_adapter; + + dvb_adapter = &dm1105dvb->dvb_adapter; + + /*dm1105dvb_read_rev(dm1105dvb); + dm1105dvb_read_serial(dm1105dvb);*/ + dm1105dvb_read_mac(dm1105dvb, dvb_adapter->proposed_mac); + + dvbdemux = &dm1105dvb->demux; + dvbdemux->filternum = 256; + dvbdemux->feednum = 256; + dvbdemux->start_feed = dm1105dvb_start_feed; + dvbdemux->stop_feed = dm1105dvb_stop_feed; + dvbdemux->dmx.capabilities = (DMX_TS_FILTERING | + DMX_SECTION_FILTERING | DMX_MEMORY_BASED_FILTERING); + ret = dvb_dmx_init(dvbdemux); + if (ret < 0) + goto err_dvb_unregister_adapter; + + dmx = &dvbdemux->dmx; + dm1105dvb->dmxdev.filternum = 256; + dm1105dvb->dmxdev.demux = dmx; + dm1105dvb->dmxdev.capabilities = 0; + + ret = dvb_dmxdev_init(&dm1105dvb->dmxdev, dvb_adapter); + if (ret < 0) + goto err_dvb_dmx_release; + + dm1105dvb->hw_frontend.source = DMX_FRONTEND_0; + + ret = dmx->add_frontend(dmx, &dm1105dvb->hw_frontend); + if (ret < 0) + goto err_dvb_dmxdev_release; + + dm1105dvb->mem_frontend.source = DMX_MEMORY_FE; + + ret = dmx->add_frontend(dmx, &dm1105dvb->mem_frontend); + if (ret < 0) + goto err_remove_hw_frontend; + + ret = dmx->connect_frontend(dmx, &dm1105dvb->hw_frontend); + if (ret < 0) + goto err_remove_mem_frontend; + + ret = frontend_init(dm1105dvb); + if (ret < 0) + goto err_disconnect_frontend; + + dvb_net_init(dvb_adapter, &dm1105dvb->dvbnet, dmx); +out: + return ret; + +err_disconnect_frontend: + dmx->disconnect_frontend(dmx); +err_remove_mem_frontend: + dmx->remove_frontend(dmx, &dm1105dvb->mem_frontend); +err_remove_hw_frontend: + dmx->remove_frontend(dmx, &dm1105dvb->hw_frontend); +err_dvb_dmxdev_release: + dvb_dmxdev_release(&dm1105dvb->dmxdev); +err_dvb_dmx_release: + dvb_dmx_release(dvbdemux); +err_dvb_unregister_adapter: + dvb_unregister_adapter(dvb_adapter); +err_i2c_del_adapter: + i2c_del_adapter(&dm1105dvb->i2c_adap); +err_dm1105dvb_hw_exit: + dm1105dvb_hw_exit(dm1105dvb); +err_free_irq: + free_irq(pdev->irq, dm1105dvb); +err_pci_iounmap: + pci_iounmap(pdev, dm1105dvb->io_mem); +err_pci_release_regions: + pci_release_regions(pdev); +err_pci_disable_device: + pci_disable_device(pdev); +err_kfree: + pci_set_drvdata(pdev, NULL); + kfree(dm1105dvb); + goto out; +} + +static void __devexit dm1105_remove(struct pci_dev *pdev) +{ + struct dm1105dvb *dm1105dvb = pci_get_drvdata(pdev); + struct dvb_adapter *dvb_adapter = &dm1105dvb->dvb_adapter; + struct dvb_demux *dvbdemux = &dm1105dvb->demux; + struct dmx_demux *dmx = &dvbdemux->dmx; + + dmx->close(dmx); + dvb_net_release(&dm1105dvb->dvbnet); + if (dm1105dvb->fe) + dvb_unregister_frontend(dm1105dvb->fe); + + dmx->disconnect_frontend(dmx); + dmx->remove_frontend(dmx, &dm1105dvb->mem_frontend); + dmx->remove_frontend(dmx, &dm1105dvb->hw_frontend); + dvb_dmxdev_release(&dm1105dvb->dmxdev); + dvb_dmx_release(dvbdemux); + dvb_unregister_adapter(dvb_adapter); + if (&dm1105dvb->i2c_adap) + i2c_del_adapter(&dm1105dvb->i2c_adap); + + dm1105dvb_hw_exit(dm1105dvb); + synchronize_irq (pdev->irq); + free_irq(pdev->irq, dm1105dvb); + pci_iounmap(pdev, dm1105dvb->io_mem); + pci_release_regions(pdev); + pci_disable_device(pdev); + pci_set_drvdata(pdev, NULL); + kfree(dm1105dvb); +} + +static struct pci_device_id dm1105_id_table[] __devinitdata = { + { + .vendor = PCI_VENDOR_ID_TRIGEM, + .device = PCI_DEVICE_ID_DM1105, + .subvendor = PCI_ANY_ID, + .subdevice = 0x2002, + }, + + { + .vendor = PCI_VENDOR_ID_TRIGEM, + .device = PCI_DEVICE_ID_DM1105, + .subvendor = PCI_ANY_ID, + .subdevice = 0x2002, + }, + + { + .vendor = PCI_VENDOR_ID_AXESS, + .device = PCI_DEVICE_ID_DM1105S, + .subvendor = PCI_ANY_ID, + .subdevice = 0x1105, + }, + + { + /* empty */ + }, +}; + +MODULE_DEVICE_TABLE(pci, dm1105_id_table); + +static struct pci_driver dm1105_driver = { + .name = DRIVER_NAME, + .id_table = dm1105_id_table, + .probe = dm1105_probe, + .remove = __devexit_p(dm1105_remove), +}; + +static int __init dm1105_init(void) +{ + return pci_register_driver(&dm1105_driver); +} + +static void __exit dm1105_exit(void) +{ + pci_unregister_driver(&dm1105_driver); +} + +module_init(dm1105_init); +module_exit(dm1105_exit); + +MODULE_AUTHOR("Igor M. Liplianin AxessMod Evgeniy R. Manachkin "); +MODULE_DESCRIPTION("DM1105/AxessDM-05 driver"); +MODULE_LICENSE("GPL"); diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/dm1105/Kconfig kernel-2.6.24.4-twinhan/drivers/media/dvb/dm1105/Kconfig --- kernel-2.6.24.4-orig/drivers/media/dvb/dm1105/Kconfig 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/dm1105/Kconfig 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,15 @@ +config DVB_DM1105 + tristate "DM1105 based cards" + depends on DVB_CORE && PCI && I2C + select DVB_PLL if !DVB_FE_CUSTOMISE + select DVB_STV0299 if !DVB_FE_CUSTOMISE + help + Support for PCI cards based on the DM1105 like the Acorp + DS110. + + Since these cards have no MPEG decoder onboard, they transmit + only compressed MPEG data over the PCI bus, so you need + an external software decoder to watch TV on your computer. + + Say Y or M if you own such a device and want to use it. + diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/dm1105/Makefile kernel-2.6.24.4-twinhan/drivers/media/dvb/dm1105/Makefile --- kernel-2.6.24.4-orig/drivers/media/dvb/dm1105/Makefile 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/dm1105/Makefile 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,3 @@ +obj-$(CONFIG_DVB_DM1105) += dm1105.o + +EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core/ -Idrivers/media/dvb/frontends diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/dvb-core/dvb_frontend.h kernel-2.6.24.4-twinhan/drivers/media/dvb/dvb-core/dvb_frontend.h --- kernel-2.6.24.4-orig/drivers/media/dvb/dvb-core/dvb_frontend.h 2008-04-05 04:21:04.000000000 +0700 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/dvb-core/dvb_frontend.h 2008-04-03 05:09:52.000000000 +0700 @@ -110,6 +110,10 @@ int (*write)(struct dvb_frontend* fe, u8* buf, int len); + /* set DvbsMode */ + int (*set_standard)(struct dvb_frontend* fe, u16* standard); + + /* if this is set, it overrides the default swzigzag */ int (*tune)(struct dvb_frontend* fe, struct dvb_frontend_parameters* params, diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/dvb-usb/dvb-usb-ids.h kernel-2.6.24.4-twinhan/drivers/media/dvb/dvb-usb/dvb-usb-ids.h --- kernel-2.6.24.4-orig/drivers/media/dvb/dvb-usb/dvb-usb-ids.h 2008-04-05 04:21:04.000000000 +0700 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/dvb-usb/dvb-usb-ids.h 2008-04-03 05:09:52.000000000 +0700 @@ -170,6 +170,7 @@ #define USB_PID_OPERA1_WARM 0x3829 #define USB_PID_LIFEVIEW_TV_WALKER_TWIN_COLD 0x0514 #define USB_PID_LIFEVIEW_TV_WALKER_TWIN_WARM 0x0513 +#define USB_PID_DW2102 0x2102 #endif diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/dvb-usb/dw2102.c kernel-2.6.24.4-twinhan/drivers/media/dvb/dvb-usb/dw2102.c --- kernel-2.6.24.4-orig/drivers/media/dvb/dvb-usb/dw2102.c 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/dvb-usb/dw2102.c 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,384 @@ +/* DVB USB framework compliant Linux driver for the DVBWorld DVB-S 2102 USB2 Card +* +* Copyright (C) 2007 Igor M. Liplianin (liplianin@me.by) +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the Free +* Software Foundation, version 2. +* +* see Documentation/dvb/README.dvb-usb for more information +*/ + +#include "dw2102.h" +#include "stv0299.h" +#include "bsru6.h" + +#define DW2102_READ_MSG 0 +#define DW2102_WRITE_MSG 1 + +#define REG_1F_SYMBOLRATE_BYTE0 0x1f +#define REG_20_SYMBOLRATE_BYTE1 0x20 +#define REG_21_SYMBOLRATE_BYTE2 0x21 + +#define DW2102_VOLTAGE_CTRL (0x1800) +#define DW2102_RC_QUERY (0x1a00) + +/* Print a warning */ +#define wprintk(fmt, arg...) \ +printk(KERN_WARNING "%s/dvb: " fmt, dev->name, ## arg) + +struct dw2102_state { +u32 last_key_pressed; +}; +struct dw2102_rc_keys { +u32 keycode; +u32 event; +}; + +int dvb_usb_dw2102_debug; +module_param_named(debug, dvb_usb_dw2102_debug, int, 0644); +MODULE_PARM_DESC(debug, + "set debugging level (1=info,xfer=2,pll=4,ts=8,err=16,rc=32,fw=64 (or-able))." + DVB_USB_DEBUG_STATUS); +static int dw2102_op_rw(struct usb_device *dev, u8 request, u16 value, + u8 * data, u16 len, int flags) +{ +int ret; +u8 u8buf[len]; + +unsigned int pipe = (flags == DW2102_READ_MSG) ? + usb_rcvctrlpipe(dev,0) : usb_sndctrlpipe(dev, 0); +u8 request_type = (flags == DW2102_READ_MSG) ? USB_DIR_IN : USB_DIR_OUT; + +if (flags == DW2102_WRITE_MSG) + memcpy(u8buf, data, len); +ret = usb_control_msg(dev, pipe, request, request_type | USB_TYPE_VENDOR, + value, 0 , u8buf, len, 2000); + +if (flags == DW2102_READ_MSG) + memcpy(data, u8buf, len); +return ret; +} + +/* I2C */ + +static int dw2102_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[], + int num) +{ +struct dvb_usb_device *d = i2c_get_adapdata(adap); +int i = 0, ret = 0; +u8 buf6[] = {0x2c,0x05,0xc0,0,0,0,0}; +u8 request; +u16 value; + +if (!d) + return -ENODEV; +if (mutex_lock_interruptible(&d->i2c_mutex) < 0) + return -EAGAIN; + +switch (num) { + case 2: + request=0xb5; + value = msg[0].buf[0]; + for (i=0; iudev, 0xb5, + value, buf6, 2, DW2102_READ_MSG); + msg[1].buf[i] = buf6[0]; + + } + break; + case 1: + switch (msg[0].addr) { + case 0x68: + buf6[0] = 0x2a; + buf6[1] = msg[0].buf[0]; + buf6[2] = msg[0].buf[1]; + ret = dw2102_op_rw(d->udev, 0xb2, + 0, buf6, 3, DW2102_WRITE_MSG); + break; + case 0x60: + if (msg[0].flags == 0) { + buf6[0] = 0x2c; + buf6[1] = 5; + buf6[2] = 0xc0; + buf6[3] = msg[0].buf[0]; + buf6[4] = msg[0].buf[1]; + buf6[5] = msg[0].buf[2]; + buf6[6] = msg[0].buf[3]; + ret = dw2102_op_rw(d->udev, 0xb2, + 0, buf6, 7, DW2102_WRITE_MSG); + } else { + ret = dw2102_op_rw(d->udev, 0xb5, + 0, buf6, 1, DW2102_READ_MSG); + msg[0].buf[0] = buf6[0]; + } + break; + case (DW2102_RC_QUERY): + ret = dw2102_op_rw(d->udev, 0xb8, + 0, buf6, 2, DW2102_READ_MSG); + msg[0].buf[0] = buf6[0]; + msg[0].buf[1] = buf6[1]; + break; + case (DW2102_VOLTAGE_CTRL): + buf6[0] = 0x30; + buf6[1] = msg[0].buf[0]; + ret = dw2102_op_rw(d->udev, 0xb2, + 0, buf6, 2, DW2102_WRITE_MSG); + break; + } + + break; +} + +mutex_unlock(&d->i2c_mutex); +return num; +} + +static u32 dw2102_i2c_func(struct i2c_adapter *adapter) +{ +return I2C_FUNC_I2C; +} + +static struct i2c_algorithm dw2102_i2c_algo = { +.master_xfer = dw2102_i2c_transfer, +.functionality = dw2102_i2c_func, +}; + +static int dw2102_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) +{ +static u8 command_13v[1]={0x00}; +static u8 command_18v[1]={0x01}; +struct i2c_msg msg[] = { + {.addr = DW2102_VOLTAGE_CTRL, .flags = 0, .buf = command_13v, .len = 1}, +}; +struct dvb_usb_adapter *udev_adap = + (struct dvb_usb_adapter *)(fe->dvb->priv); +if (voltage == SEC_VOLTAGE_18) { + msg[0].buf = command_18v; +} +i2c_transfer(&udev_adap->dev->i2c_adap, msg, 1); +return 0; +} + +static int dw2102_frontend_attach(struct dvb_usb_adapter *d) +{ +if ((d->fe = + dvb_attach(stv0299_attach, &alps_bsru6_config, + &d->dev->i2c_adap)) != NULL) { + d->fe->ops.set_voltage = dw2102_set_voltage; + info("Attached stv0299!\n"); + return 0; +} +return -EIO; +} + +static int dw2102_tuner_attach(struct dvb_usb_adapter *adap) +{ +dvb_attach( + dvb_pll_attach, adap->fe, 0x60, + &adap->dev->i2c_adap, DVB_PLL_OPERA1 +); +return 0; +} + +static struct dvb_usb_rc_key dw2102_rc_keys[] = { +{ 0xf8, 0x0a, KEY_Q }, /*power*/ +{ 0xf8, 0x0c, KEY_M }, /*mute*/ +{ 0xf8, 0x11, KEY_1 }, +{ 0xf8, 0x12, KEY_2 }, +{ 0xf8, 0x13, KEY_3 }, +{ 0xf8, 0x14, KEY_4 }, +{ 0xf8, 0x15, KEY_5 }, +{ 0xf8, 0x16, KEY_6 }, +{ 0xf8, 0x17, KEY_7 }, +{ 0xf8, 0x18, KEY_8 }, +{ 0xf8, 0x19, KEY_9 }, +{ 0xf8, 0x10, KEY_0 }, +{ 0xf8, 0x1c, KEY_PAGEUP }, /*ch+*/ +{ 0xf8, 0x0f, KEY_PAGEDOWN }, /*ch-*/ +{ 0xf8, 0x1a, KEY_O }, /*vol+*/ +{ 0xf8, 0x0e, KEY_Z }, /*vol-*/ +{ 0xf8, 0x04, KEY_R }, /*rec*/ +{ 0xf8, 0x09, KEY_D }, /*fav*/ +{ 0xf8, 0x08, KEY_BACKSPACE }, /*rewind*/ +{ 0xf8, 0x07, KEY_A }, /*fast*/ +{ 0xf8, 0x0b, KEY_P }, /*pause*/ +{ 0xf8, 0x02, KEY_ESC }, /*cancel*/ +{ 0xf8, 0x03, KEY_G }, /*tab*/ +{ 0xf8, 0x00, KEY_UP }, /*up*/ +{ 0xf8, 0x1f, KEY_ENTER }, /*ok*/ +{ 0xf8, 0x01, KEY_DOWN }, /*down*/ +{ 0xf8, 0x05, KEY_C }, /*cap*/ +{ 0xf8, 0x06, KEY_S }, /*stop*/ +{ 0xf8, 0x40, KEY_F }, /*full*/ +{ 0xf8, 0x1e, KEY_W }, /*tvmode*/ +{ 0xf8, 0x1b, KEY_P }, /*recall*/ + +}; + + + +static int dw2102_rc_query(struct dvb_usb_device *d, u32 *event, int *state) +{ +struct dw2102_state *st = d->priv; +u8 key[2]; +struct i2c_msg msg[] = { + {.addr = DW2102_RC_QUERY, .flags = I2C_M_RD, .buf = key, .len = 2}, +}; +int i = 0; + +*state = REMOTE_NO_KEY_PRESSED; +if (dw2102_i2c_transfer(&d->i2c_adap, msg, 1)==1) { + for (i = 0; i < ARRAY_SIZE(dw2102_rc_keys); i++) { + if (dw2102_rc_keys[i].data == msg[0].buf[0]) { + *state = REMOTE_KEY_PRESSED; + *event = dw2102_rc_keys[i].event; + st->last_key_pressed = + dw2102_rc_keys[i].event; + break; + } + st->last_key_pressed = 0; + } +} +/* info("key: %x %x\n",key[0],key[1]); */ +return 0; +} + +static struct usb_device_id dw2102_table[] = { +{USB_DEVICE(USB_VID_CYPRESS, USB_PID_DW2102)}, +{0} +}; + +MODULE_DEVICE_TABLE(usb, dw2102_table); + +static int dw2102_load_firmware(struct usb_device *dev, + const struct firmware *fw) +{ +u8 *b, *p; +int ret = 0, i; +u8 reset; +u8 reset16 [] = {0,0}; +info("start downloading DW2102 firmware"); +p = kmalloc(fw->size, GFP_KERNEL); +reset = 1; +/*stop the CPU*/ +dw2102_op_rw(dev, 0xa0, 0x7f92, &reset, 1, DW2102_WRITE_MSG); +dw2102_op_rw(dev, 0xa0, 0xe600, &reset, 1, DW2102_WRITE_MSG); + +if (p != NULL) { + memcpy(p, fw->data, fw->size); + for (i = 0; i < fw->size; i += 0x40) { + b = (u8 *) p + i; + if (dw2102_op_rw + (dev, 0xa0, i, b , 0x40, + DW2102_WRITE_MSG) != 0x40 + ) { + err("error while transferring firmware"); + ret = -EINVAL; + break; + } + } + /* restart the CPU */ + reset = 0; + if (ret || dw2102_op_rw + (dev, 0xa0, 0x7f92, &reset, 1, + DW2102_WRITE_MSG) != 1) { + err("could not restart the USB controller CPU."); + ret = -EINVAL; + } + if (ret || dw2102_op_rw + (dev, 0xa0, 0xe600, &reset, 1, + DW2102_WRITE_MSG) != 1) { + err("could not restart the USB controller CPU."); + ret = -EINVAL; + } + dw2102_op_rw + (dev, 0xbf, 0x0040, &reset, 0, + DW2102_WRITE_MSG); + dw2102_op_rw + (dev, 0xb9, 0x0000, &reset16[0], 2, + DW2102_READ_MSG); + + kfree(p); +} +return ret; +} + +static struct dvb_usb_device_properties dw2102_properties = { +.caps = DVB_USB_IS_AN_I2C_ADAPTER, +.usb_ctrl = DEVICE_SPECIFIC, +.firmware = "dvb-usb-dw2102.fw", +.size_of_priv = sizeof(struct dw2102_state), +.no_reconnect = 1, + +.i2c_algo = &dw2102_i2c_algo, +.rc_key_map = dw2102_rc_keys, +.rc_key_map_size = ARRAY_SIZE(dw2102_rc_keys), +.rc_interval = 150, +.rc_query = dw2102_rc_query, + +.generic_bulk_ctrl_endpoint = 0x81, +/* parameter for the MPEG2-data transfer */ +.num_adapters = 1, +.download_firmware = dw2102_load_firmware, +.adapter = { + { + .frontend_attach = dw2102_frontend_attach, + .streaming_ctrl = NULL, + .tuner_attach = dw2102_tuner_attach, + .stream = { + .type = USB_BULK, + .count = 8, + .endpoint = 0x82, + .u = { + .bulk = { + .buffersize = 4096, + } + } + }, + } +}, +.num_device_descs = 1, +.devices = { + {"DVBWorld DVB-S 2102 USB2.0", + {&dw2102_table[0], NULL}, + }, + {NULL}, +} +}; + +static int dw2102_probe(struct usb_interface *intf, + const struct usb_device_id *id) +{ +return dvb_usb_device_init(intf, &dw2102_properties, THIS_MODULE, NULL); +} + +static struct usb_driver dw2102_driver = { +.name = "dw2102", +.probe = dw2102_probe, +.disconnect = dvb_usb_device_exit, +.id_table = dw2102_table, +}; + +static int __init dw2102_module_init(void) +{ +int result = 0; +if ((result = usb_register(&dw2102_driver))) { + err("usb_register failed. Error number %d", result); +} +return result; +} + +static void __exit dw2102_module_exit(void) +{ +usb_deregister(&dw2102_driver); +} + +module_init(dw2102_module_init); +module_exit(dw2102_module_exit); + +MODULE_AUTHOR("Igor M. Liplianin (c) liplianin@me.by"); +MODULE_DESCRIPTION("Driver for DVBWorld DVB-S 2102 USB2.0 device"); +MODULE_VERSION("0.1"); +MODULE_LICENSE("GPL"); diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/dvb-usb/dw2102.h kernel-2.6.24.4-twinhan/drivers/media/dvb/dvb-usb/dw2102.h --- kernel-2.6.24.4-orig/drivers/media/dvb/dvb-usb/dw2102.h 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/dvb-usb/dw2102.h 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,9 @@ +#ifndef _DW2102_H_ +#define _DW2102_H_ + +#define DVB_USB_LOG_PREFIX "dw2102" +#include "dvb-usb.h" + +extern int dvb_usb_dw2102_debug; +#define deb_xfer(args...) dprintk(dvb_usb_dw2102_debug,0x02,args) +#endif diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/dvb-usb/Kconfig kernel-2.6.24.4-twinhan/drivers/media/dvb/dvb-usb/Kconfig --- kernel-2.6.24.4-orig/drivers/media/dvb/dvb-usb/Kconfig 2008-04-05 04:21:04.000000000 +0700 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/dvb-usb/Kconfig 2008-04-03 05:09:52.000000000 +0700 @@ -239,3 +239,10 @@ Say Y here to support the default remote control decoding for the Afatech AF9005 based receiver. +config DVB_USB_DW2102 + tristate "DvbWorld 2102 DVB-S USB2.0 receiver" + depends on DVB_USB + select DVB_STV0299 if !DVB_FE_CUSTOMISE + select DVB_PLL if !DVB_FE_CUSTOMISE + help + Say Y here to support the DvbWorld 2102 DVB-S USB2.0 receiver. diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/dvb-usb/Makefile kernel-2.6.24.4-twinhan/drivers/media/dvb/dvb-usb/Makefile --- kernel-2.6.24.4-orig/drivers/media/dvb/dvb-usb/Makefile 2008-04-05 04:21:04.000000000 +0700 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/dvb-usb/Makefile 2008-04-03 05:09:52.000000000 +0700 @@ -61,6 +61,9 @@ dvb-usb-af9005-remote-objs = af9005-remote.o obj-$(CONFIG_DVB_USB_AF9005_REMOTE) += dvb-usb-af9005-remote.o +dvb-usb-dw2102-objs = dw2102.o +obj-$(CONFIG_DVB_USB_DW2102) += dvb-usb-dw2102.o + EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core/ -Idrivers/media/dvb/frontends/ # due to tuner-xc3028 EXTRA_CFLAGS += -Idrivers/media/video diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/frontends/at76c651.c kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/at76c651.c --- kernel-2.6.24.4-orig/drivers/media/dvb/frontends/at76c651.c 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/at76c651.c 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,439 @@ +/* + * at76c651.c + * + * Atmel DVB-C Frontend Driver (at76c651/tua6010xs) + * + * Copyright (C) 2001 fnbrd + * & 2002-2004 Andreas Oberritter + * & 2003 Wolfram Joost + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * AT76C651 + * http://www.nalanda.nitc.ac.in/industry/datasheets/atmel/acrobat/doc1293.pdf + * http://www.atmel.com/atmel/acrobat/doc1320.pdf + */ + +#include +#include +#include +#include +#include +#include +#include +#include "dvb_frontend.h" +#include "at76c651.h" + + +struct at76c651_state { + + struct i2c_adapter* i2c; + + const struct at76c651_config* config; + + struct dvb_frontend frontend; + + /* revision of the chip */ + u8 revision; + + /* last QAM value set */ + u8 qam; +}; + +static int debug; +#define dprintk(args...) \ + do { \ + if (debug) printk(KERN_DEBUG "at76c651: " args); \ + } while (0) + + +static int at76c651_writereg(struct at76c651_state* state, u8 reg, u8 data) +{ + int ret; + u8 buf[] = { reg, data }; + struct i2c_msg msg = + { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 }; + + ret = i2c_transfer(state->i2c, &msg, 1); + + if (ret != 1) + dprintk("%s: writereg error " + "(reg == 0x%02x, val == 0x%02x, ret == %i)\n", + __FUNCTION__, reg, data, ret); + + msleep(10); + + return (ret != 1) ? -EREMOTEIO : 0; +} + +static u8 at76c651_readreg(struct at76c651_state* state, u8 reg) +{ + int ret; + u8 val; + struct i2c_msg msg[] = { + { .addr = state->config->demod_address, .flags = 0, .buf = ®, .len = 1 }, + { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = &val, .len = 1 } + }; + + ret = i2c_transfer(state->i2c, msg, 2); + + if (ret != 2) + dprintk("%s: readreg error (ret == %i)\n", __FUNCTION__, ret); + + return val; +} + +static int at76c651_reset(struct at76c651_state* state) +{ + return at76c651_writereg(state, 0x07, 0x01); +} + +static void at76c651_disable_interrupts(struct at76c651_state* state) +{ + at76c651_writereg(state, 0x0b, 0x00); +} + +static int at76c651_set_auto_config(struct at76c651_state *state) +{ + /* + * Autoconfig + */ + + at76c651_writereg(state, 0x06, 0x01); + + /* + * Performance optimizations, should be done after autoconfig + */ + + at76c651_writereg(state, 0x10, 0x06); + at76c651_writereg(state, 0x11, ((state->qam == 5) || (state->qam == 7)) ? 0x12 : 0x10); + at76c651_writereg(state, 0x15, 0x28); + at76c651_writereg(state, 0x20, 0x09); + at76c651_writereg(state, 0x24, ((state->qam == 5) || (state->qam == 7)) ? 0xC0 : 0x90); + at76c651_writereg(state, 0x30, 0x90); + if (state->qam == 5) + at76c651_writereg(state, 0x35, 0x2A); + + /* + * Initialize A/D-converter + */ + + if (state->revision == 0x11) { + at76c651_writereg(state, 0x2E, 0x38); + at76c651_writereg(state, 0x2F, 0x13); + } + + at76c651_disable_interrupts(state); + + /* + * Restart operation + */ + + at76c651_reset(state); + + return 0; +} + +static void at76c651_set_bbfreq(struct at76c651_state* state) +{ + at76c651_writereg(state, 0x04, 0x3f); + at76c651_writereg(state, 0x05, 0xee); +} + +static int at76c651_set_symbol_rate(struct at76c651_state* state, u32 symbol_rate) +{ + u8 exponent; + u32 mantissa; + + if (symbol_rate > 9360000) + return -EINVAL; + + /* + * FREF = 57800 kHz + * exponent = 10 + floor (log2(symbol_rate / FREF)) + * mantissa = (symbol_rate / FREF) * (1 << (30 - exponent)) + */ + + exponent = long_log2((symbol_rate << 4) / 903125); + mantissa = ((symbol_rate / 3125) * (1 << (24 - exponent))) / 289; + + at76c651_writereg(state, 0x00, mantissa >> 13); + at76c651_writereg(state, 0x01, mantissa >> 5); + at76c651_writereg(state, 0x02, (mantissa << 3) | exponent); + + return 0; +} + +static int at76c651_set_qam(struct at76c651_state *state, fe_modulation_t qam) +{ + switch (qam) { + case QPSK: + state->qam = 0x02; + break; + case QAM_16: + state->qam = 0x04; + break; + case QAM_32: + state->qam = 0x05; + break; + case QAM_64: + state->qam = 0x06; + break; + case QAM_128: + state->qam = 0x07; + break; + case QAM_256: + state->qam = 0x08; + break; +#if 0 /* keep */ + case QAM_512: + state->qam = 0x09; + break; + case QAM_1024: + state->qam = 0x0A; + break; +#endif + default: + return -EINVAL; + + } + + return at76c651_writereg(state, 0x03, state->qam); +} + +static int at76c651_set_inversion(struct at76c651_state* state, fe_spectral_inversion_t inversion) +{ + u8 feciqinv = at76c651_readreg(state, 0x60); + + switch (inversion) { + case INVERSION_OFF: + feciqinv |= 0x02; + feciqinv &= 0xFE; + break; + + case INVERSION_ON: + feciqinv |= 0x03; + break; + + case INVERSION_AUTO: + feciqinv &= 0xFC; + break; + + default: + return -EINVAL; + } + + return at76c651_writereg(state, 0x60, feciqinv); +} + +static int at76c651_set_parameters(struct dvb_frontend* fe, + struct dvb_frontend_parameters *p) +{ + int ret; + struct at76c651_state* state = fe->demodulator_priv; + + if (fe->ops.tuner_ops.set_params) { + fe->ops.tuner_ops.set_params(fe, p); + if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); + } + + if ((ret = at76c651_set_symbol_rate(state, p->u.qam.symbol_rate))) + return ret; + + if ((ret = at76c651_set_inversion(state, p->inversion))) + return ret; + + return at76c651_set_auto_config(state); +} + +static int at76c651_set_defaults(struct dvb_frontend* fe) +{ + struct at76c651_state* state = fe->demodulator_priv; + + at76c651_set_symbol_rate(state, 6900000); + at76c651_set_qam(state, QAM_64); + at76c651_set_bbfreq(state); + at76c651_set_auto_config(state); + + return 0; +} + +static int at76c651_read_status(struct dvb_frontend* fe, fe_status_t* status) +{ + struct at76c651_state* state = fe->demodulator_priv; + u8 sync; + + /* + * Bits: FEC, CAR, EQU, TIM, AGC2, AGC1, ADC, PLL (PLL=0) + */ + sync = at76c651_readreg(state, 0x80); + *status = 0; + + if (sync & (0x04 | 0x10)) /* AGC1 || TIM */ + *status |= FE_HAS_SIGNAL; + if (sync & 0x10) /* TIM */ + *status |= FE_HAS_CARRIER; + if (sync & 0x80) /* FEC */ + *status |= FE_HAS_VITERBI; + if (sync & 0x40) /* CAR */ + *status |= FE_HAS_SYNC; + if ((sync & 0xF0) == 0xF0) /* TIM && EQU && CAR && FEC */ + *status |= FE_HAS_LOCK; + + return 0; +} + +static int at76c651_read_ber(struct dvb_frontend* fe, u32* ber) +{ + struct at76c651_state* state = fe->demodulator_priv; + + *ber = (at76c651_readreg(state, 0x81) & 0x0F) << 16; + *ber |= at76c651_readreg(state, 0x82) << 8; + *ber |= at76c651_readreg(state, 0x83); + *ber *= 10; + + return 0; +} + +static int at76c651_read_signal_strength(struct dvb_frontend* fe, u16* strength) +{ + struct at76c651_state* state = fe->demodulator_priv; + + u8 gain = ~at76c651_readreg(state, 0x91); + *strength = (gain << 8) | gain; + + return 0; +} + +static int at76c651_read_snr(struct dvb_frontend* fe, u16* snr) +{ + struct at76c651_state* state = fe->demodulator_priv; + + *snr = 0xFFFF - + ((at76c651_readreg(state, 0x8F) << 8) | + at76c651_readreg(state, 0x90)); + + return 0; +} + +static int at76c651_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) +{ + struct at76c651_state* state = fe->demodulator_priv; + + *ucblocks = at76c651_readreg(state, 0x82); + + return 0; +} + +static int at76c651_i2c_gate_ctrl(struct dvb_frontend* fe, int enable) +{ + struct at76c651_state* state = fe->demodulator_priv; + + if (enable) { + return at76c651_writereg(state, 0x0c, 0xc3); + } else { + return at76c651_writereg(state, 0x0c, 0xc2); + } +} + +static int at76c651_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *fesettings) +{ + fesettings->min_delay_ms = 50; + fesettings->step_size = 0; + fesettings->max_drift = 0; + return 0; +} + +static void at76c651_release(struct dvb_frontend* fe) +{ + struct at76c651_state* state = fe->demodulator_priv; + kfree(state); +} + +static struct dvb_frontend_ops at76c651_ops; + +struct dvb_frontend* at76c651_attach(const struct at76c651_config* config, + struct i2c_adapter* i2c) +{ + struct at76c651_state* state = NULL; + + /* allocate memory for the internal state */ + state = kmalloc(sizeof(struct at76c651_state), GFP_KERNEL); + if (state == NULL) goto error; + + /* setup the state */ + state->config = config; + state->qam = 0; + + /* check if the demod is there */ + if (at76c651_readreg(state, 0x0e) != 0x65) goto error; + + /* finalise state setup */ + state->i2c = i2c; + state->revision = at76c651_readreg(state, 0x0f) & 0xfe; + + /* create dvb_frontend */ + memcpy(&state->frontend.ops, &at76c651_ops, sizeof(struct dvb_frontend_ops)); + state->frontend.demodulator_priv = state; + return &state->frontend; + +error: + kfree(state); + return NULL; +} + +static struct dvb_frontend_ops at76c651_ops = { + + .info = { + .name = "Atmel AT76C651B DVB-C", + .type = FE_QAM, + .frequency_min = 48250000, + .frequency_max = 863250000, + .frequency_stepsize = 62500, + /*.frequency_tolerance = */ /* FIXME: 12% of SR */ + .symbol_rate_min = 0, /* FIXME */ + .symbol_rate_max = 9360000, /* FIXME */ + .symbol_rate_tolerance = 4000, + .caps = FE_CAN_INVERSION_AUTO | + FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | + FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | + FE_CAN_FEC_7_8 | FE_CAN_FEC_8_9 | FE_CAN_FEC_AUTO | + FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | FE_CAN_QAM_128 | + FE_CAN_MUTE_TS | FE_CAN_QAM_256 | FE_CAN_RECOVER + }, + + .release = at76c651_release, + + .init = at76c651_set_defaults, + .i2c_gate_ctrl = at76c651_i2c_gate_ctrl, + + .set_frontend = at76c651_set_parameters, + .get_tune_settings = at76c651_get_tune_settings, + + .read_status = at76c651_read_status, + .read_ber = at76c651_read_ber, + .read_signal_strength = at76c651_read_signal_strength, + .read_snr = at76c651_read_snr, + .read_ucblocks = at76c651_read_ucblocks, +}; + +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); + +MODULE_DESCRIPTION("Atmel AT76C651 DVB-C Demodulator Driver"); +MODULE_AUTHOR("Andreas Oberritter "); +MODULE_LICENSE("GPL"); + +EXPORT_SYMBOL(at76c651_attach); diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/frontends/at76c651.h kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/at76c651.h --- kernel-2.6.24.4-orig/drivers/media/dvb/frontends/at76c651.h 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/at76c651.h 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,52 @@ +/* + * at76c651.c + * + * Atmel DVB-C Frontend Driver (at76c651) + * + * Copyright (C) 2001 fnbrd + * & 2002-2004 Andreas Oberritter + * & 2003 Wolfram Joost + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * AT76C651 + * http://www.nalanda.nitc.ac.in/industry/datasheets/atmel/acrobat/doc1293.pdf + * http://www.atmel.com/atmel/acrobat/doc1320.pdf + */ + +#ifndef AT76C651_H +#define AT76C651_H + +#include + +struct at76c651_config +{ + /* the demodulator's i2c address */ + u8 demod_address; +}; + +#if defined(CONFIG_DVB_AT76C651) || defined(CONFIG_DVB_AT76C651_MODULE) +extern struct dvb_frontend* at76c651_attach(const struct at76c651_config* config, + struct i2c_adapter* i2c); +#else +static inline struct dvb_frontend* at76c651_attach(const struct at76c651_config* config, + struct i2c_adapter* i2c) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __FUNCTION__); + return NULL; +} +#endif // CONFIG_DVB_AT76C651 + +#endif // AT76C651_H diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/frontends/cu1216.c kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/cu1216.c --- kernel-2.6.24.4-orig/drivers/media/dvb/frontends/cu1216.c 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/cu1216.c 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,1531 @@ +/* + CU-1216 driver for the Mantis bridge based cards + + Copyright (C) 2005 Twinhan Technology Co. Ltd + based on the TDA 10021 driver + + Copyright (C) 1999 Convergence Integrated Media GmbH + Copyright (C) 2004 Markus Schulz + + Copyright (C) 2005, 2006 Manu Abraham (abraham.manu@gmail.com) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +//#include +#include +#include +#include +#include +#include +#include +#include + +#include "dvb_frontend.h" +#include "../mantis/mantis_core.h" +#include "cu1216.h" +#include "cu1216_regs.h" + +unsigned int verbose = 1; +unsigned char type; //TDA10021 or TDA10023 +module_param(verbose, int, 0644); +MODULE_PARM_DESC(verbose, "print AFC offset after tuning for debugging the PWM setting"); + + +typedef struct AC_TypeQAM_TAG { + u8 bConf; + u8 bAgcref; + u8 bLockthr; + u8 bMseth; + u8 bAref; +} AC_TypeQAM_T; + +typedef struct TDA10023_QAM_TAG{ + u8 uQam; + u8 uLockthr; + u8 uMseth; + u8 uAref; + u8 uAgcRefNyq; + u8 uErAgcNyqThd; +} TDA10023Qam_t; + +static void cu1216_set_symbolRate(struct dvb_frontend *fe, u16 uFreqSymb); +static void cu1216_set_QAM (struct dvb_frontend *fe, u8 bQAM); +static void cu1216_set_IQ (struct dvb_frontend *fe, u8 bSI); +static void cu1216_set_gain (struct dvb_frontend *fe, u8 bGain); +static void cu1216_clear_register(struct dvb_frontend *fe); +static int cu1216_init (struct dvb_frontend *fe); +static int tda10023_set_tuner(struct dvb_frontend *fe, struct dvb_frontend_parameters *params); +static int tda10023_writereg (struct cu1216_state *state, u8 reg, u8 data); + + +static int tda10023_writereg (struct cu1216_state *state, u8 reg, u8 data) +{ + u8 buf[] = { reg, data }; + int ret; + + struct i2c_msg msg = { + .addr = 0xc0 << 1, + .flags = 0, + .buf = buf, + .len = 2 + }; + + ret = i2c_transfer (state->i2c, &msg, 1); + if (ret != 1) + printk("DVB: TDA10023(%d): %s, writereg error ""(reg == 0x%02x, val == 0x%02x, ret == %i)\n", state->frontend.dvb->num, __FUNCTION__, reg, data, ret); + + msleep(10); + return (ret != 1) ? -EREMOTEIO : 0; +} + +static int cu1216_writereg (struct cu1216_state *state, u8 reg, u8 data) +{ + u8 buf[] = { reg, data }; + + struct i2c_msg msg = { + .addr = state->config->demod_address, + .flags = 0, + .buf = buf, + .len = 2 + }; + int ret; + + ret = i2c_transfer (state->i2c, &msg, 1); + if (ret != 1) + printk("DVB: TDA10021(%d): %s, writereg error ""(reg == 0x%02x, val == 0x%02x, ret == %i)\n", state->frontend.dvb->num, __FUNCTION__, reg, data, ret); + + msleep(10); + return (ret != 1) ? -EREMOTEIO : 0; +} + +static u8 cu1216_readreg (struct cu1216_state *state, u8 reg) +{ + u8 b0 [] = { reg }; + u8 b1 [] = { 0 }; + struct i2c_msg msg [] = { + { + .addr = state->config->demod_address, + .flags = 0, + .buf = b0, + .len = 1 + }, + { + .addr = state->config->demod_address, + .flags = I2C_M_RD, + .buf = b1, + .len = 1 + } + }; + int ret; + + ret = i2c_transfer (state->i2c, msg, 2); + if (ret != 2) + printk("DVB: TDA10021: %s: readreg error (ret == %i)\n",__FUNCTION__, ret); + return b1[0]; +} + +static int cu1216_writereg_mask (struct cu1216_state *state, u8 reg, u8 mask, u8 data) +{ + u8 value; + + value = cu1216_readreg(state, reg); + value = (value & ~mask) | (data & mask); + + return cu1216_writereg(state, reg, value); +} + + +//get access to tuner +static int lock_tuner(struct cu1216_state *state) +{ + u8 buf[2] = { 0x0f, 0x40 | 0x80 }; + struct i2c_msg msg = { + .addr = state->config->demod_address, + .flags = 0, + .buf = buf, + .len = 2 + }; + + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk("cu1216: lock tuner fails\n"); + return -EREMOTEIO; + } + return 0; +} + +//release access from tuner +static int unlock_tuner(struct cu1216_state *state) +{ + u8 buf[2] = { 0x0f, 0x40 & 0x7f }; + struct i2c_msg msg_post = { + .addr = state->config->demod_address, + .flags = 0, + .buf = buf, + .len = 2 + }; + + if (i2c_transfer(state->i2c, &msg_post, 1) != 1) { + printk("cu1216: unlock tuner fails\n"); + return -EREMOTEIO; + } + + return 0; +} + +static void cu1216_set_symbolRate(struct dvb_frontend *fe, u16 uFreqSymb) +{ + struct cu1216_state *state = fe->demodulator_priv; + + u8 pWrite[4], bNdec, bSFil; + u32 uBDR, uBDRb ,uFreqSymbInv, uFreqSymb480; + u32 uSR,uSysClk; + u32 fSysClk; + + if(uFreqSymb == 0) + return ; + + if(type == MK1) + { + // calculate the system frequency + fSysClk = OM5734_XTALFREQ_DEF * (OM5734_PLLMFACTOR_DEF + 1); + fSysClk /= (OM5734_PLLNFACTOR_DEF + 1) * (OM5734_PLLPFACTOR_DEF + 1); + + // add 480 ppm to the SR + uFreqSymb480 = uFreqSymb; + uFreqSymb480 = uFreqSymb * 480; // I Don't Know why it * 480 not + 480 + uFreqSymb480 /= 1000000L; + uFreqSymb480 = uFreqSymb + uFreqSymb480; + fSysClk = fSysClk/1000; + bNdec = 0; + bSFil = 1; + + if (((fSysClk / 123) < (uFreqSymb480 / 10)) && ((uFreqSymb480 / 10) <= (fSysClk / 80))) + bSFil = 0; + + if (((fSysClk / 246) < (uFreqSymb480 / 10)) && ((uFreqSymb480 / 10) <= (fSysClk / 160))) + bSFil = 0; + + if (((fSysClk / 492) < (uFreqSymb480 / 10)) && ((uFreqSymb480 / 10) <= (fSysClk / 320))) + bSFil = 0; + + if (((fSysClk / 984) < (uFreqSymb480 / 10)) && ((uFreqSymb480 / 10) <= (fSysClk / 640))) + bSFil = 0; + + // program SFIL + cu1216_writereg(state, AC_GAIN_IND, 0x23); + + // program NDEC + cu1216_writereg(state, AC_CLKCONF_IND, 0x0a); + + //--------------------------------------- + // program the symbol frequency registers + //--------------------------------------- + // calculate the inversion of the symbol frequency + uFreqSymbInv = fSysClk * 16; // prefer to P21/58 Ice_Deng 2003/12/20 + uFreqSymbInv >>= bNdec; // divide by 2^decim + uFreqSymbInv += uFreqSymb / 2; // rounding for division + uFreqSymbInv /= uFreqSymb; + + if (uFreqSymbInv > 255) + uFreqSymbInv = 255; + + uBDRb = 1; + uBDRb = uBDRb << (24 + bNdec); + + fSysClk = fSysClk / 10; + uBDR = uBDRb / fSysClk; + uBDR *= uFreqSymb; + + uBDRb %= fSysClk; + uBDRb *= uFreqSymb; + uBDRb /= fSysClk; + uBDR += uBDRb; + uBDR /= 10; + + // program the value in register of the symbol rate + pWrite[0] = (unsigned char)(uBDR); + pWrite[1] = (unsigned char)(uBDR >> 8); + pWrite[2] = (unsigned char)(uBDR >> 16); + pWrite[3] = (unsigned char)uFreqSymbInv; + + cu1216_writereg(state, AC_BDRLSB_IND, pWrite[0]); + cu1216_writereg(state, AC_BDRMID_IND, pWrite[1]); + cu1216_writereg(state, AC_BDRMSB_IND, pWrite[2]); + cu1216_writereg(state, AC_BDRINV_IND, pWrite[3]); + } + else + { + uSR = uFreqSymb; + // calculate the system frequency + uSysClk = CU1216_XTALL_FREQ_28 * (CU1216_PLLMFACTOR_DVB_DEF+1); + uSysClk /= (CU1216_PLLNFACTOR_DVB_DEF+1)*(CU1216_PLLPFACTOR_DVB_DEF+1); + uSysClk /=1000; + + if (uSR/10 < uSysClk/984) + { + bNdec = 3; + bSFil = 1; + } + else if (uSR/10 < uSysClk/640) + { + bNdec = 3; + bSFil = 0; + } + else if (uSR/10 < uSysClk/492) + { + bNdec = 2; + bSFil = 1; + } + else if (uSR/10 < uSysClk/320) + { + bNdec = 2; + bSFil = 0; + } + else if (uSR/10 < uSysClk/246) + { + bNdec = 1; + bSFil = 1; + } + else if (uSR/10 < uSysClk/160) + { + bNdec = 1; + bSFil = 0; + } + else if (uSR/10 < uSysClk/123) + { + bNdec = 0; + bSFil = 1; + } + else + { + bNdec = 0; + bSFil = 0; + } + // program SFIL + cu1216_writereg_mask( state, 0x3d, 0x80, bSFil << 7); + + // program NDEC + cu1216_writereg_mask( state, 0x03, 0xc0, bNdec << 6); + + //--------------------------------------- + // program the symbol frequency registers + //--------------------------------------- + // calculate the inversion of the symbol frequency + uFreqSymbInv = uSysClk*16; + uFreqSymbInv >>= bNdec; + uFreqSymbInv += uFreqSymb/2; + uFreqSymbInv /= uFreqSymb; + if (uFreqSymbInv > 255) + { + uFreqSymbInv = 255; + } + // calculate the symbol rate + uBDRb=1; + uBDRb = uBDRb<<(24+bNdec); + uSysClk=uSysClk/10; + uBDR = uBDRb/uSysClk; + uBDR *= uFreqSymb; + + uBDRb %=uSysClk; + uBDRb *= uFreqSymb; + uBDRb /= uSysClk; + uBDR +=uBDRb; + uBDR /=10; + + // program the value in register of the symbol rate + pWrite[0] = (u8)(uBDR); + pWrite[1] = (u8)(uBDR >> 8); + pWrite[2] = (u8)(uBDR >> 16); + pWrite[3] = (u8)uFreqSymbInv; + + cu1216_writereg(state, AC_BDRLSB_IND, pWrite[0]); + cu1216_writereg(state, AC_BDRMID_IND, pWrite[1]); + cu1216_writereg(state, AC_BDRMSB_IND, pWrite[2]); + cu1216_writereg(state, AC_BDRINV_IND, pWrite[3]); + } + +} + + +static void cu1216_set_QAM(struct dvb_frontend *fe, u8 bQAM) // The default value is 16 --QAM +{ + struct cu1216_state *state = fe->demodulator_priv; + + if(type == MK1) + { + AC_TypeQAM_T sTypeQAM[] = { + { 0x14, 120, 0x78, 114, 0x96 }, // 4 QAM <=> qam=0 + { 0x00, 140, 0x6e, 162, 0x91 }, // 16 QAM <=> qam=1 + { 0x04, 140, 0x4b, 116, 0x96 }, // 32 QAM <=> qam=2 + { 0x08, 106, 0x37, 67, 0x6a }, // 64 QAM <=> qam=3 + { 0x0c, 120, 0x2d, 52, 0x7e }, // 128 QAM <=> qam=4 + { 0x10, 92, 0x23, 35, 0x6b }, // 256 QAM <=> qam=5 + }; + + // program the modulation in CONF register + cu1216_writereg_mask(state, AC_CONF_IND, AC_CONF_QAM_MSK, sTypeQAM[bQAM].bConf); + // AGCREF + cu1216_writereg(state, AC_AGCREF_IND, sTypeQAM[bQAM].bAgcref); + // LOCKTHR + cu1216_writereg(state, AC_LOCKTHR_IND, sTypeQAM[bQAM].bLockthr); + // MSETH + cu1216_writereg(state, AC_MSETH_IND, sTypeQAM[bQAM].bMseth); + // AREF + cu1216_writereg(state, AC_AREF_IND, sTypeQAM[bQAM].bAref); + } + else + { + + // QAM LOCKTHR MSETH AREF AGCREFNYQ ERAGCNYQ_THD + static TDA10023Qam_t sTypeQAM3[] = { + { 0x14, 0x78, 0x8c, 0x96, 0x78, 0x4c },// 4 QAM <=> qam=0 + { 0x00, 0x87, 0xa2, 0x91, 0x8c, 0x57 },// 16 QAM <=> qam=1 + { 0x04, 0x64, 0x74, 0x96, 0x8c, 0x57 },// 32 QAM <=> qam=2 + { 0x08, 0x46, 0x43, 0x6a, 0x6a, 0x44 },// 64 QAM <=> qam=3 + { 0x0c, 0x36, 0x34, 0x7e, 0x78, 0x4c },// 128 QAM<=> qam=4 + { 0x10, 0x26, 0x23, 0x6c, 0x5c, 0x3c } // 256 QAM<=> qam=5 + }; + + // LOCKTHR + cu1216_writereg( state,0x05 , sTypeQAM3[bQAM].uLockthr) ; + // MSETH + cu1216_writereg( state,0x08 , sTypeQAM3[bQAM].uMseth) ; + // AREF + cu1216_writereg( state,0x09 , sTypeQAM3[bQAM].uAref) ; + // AGCREFNYQ + cu1216_writereg( state,TDA10023_AGCREFNYQ_IND , sTypeQAM3[bQAM].uAgcRefNyq) ; + // ERAGCNYQ_THD + cu1216_writereg( state,TDA10023_ERAGCNYQ_THD_IND , sTypeQAM3[bQAM].uErAgcNyqThd) ; + + // GPR: program the modulation in QAM bits + cu1216_writereg_mask( state,0x00, 0x1c,sTypeQAM3[bQAM].uQam); + + }//end else mk3 +} + +static void cu1216_set_IQ(struct dvb_frontend *fe, u8 bSI) +{ + struct cu1216_state *state = fe->demodulator_priv; + + // set the spectral inversion mode + bSI = (bSI+1)%2; + + // write the ConfReg Register + cu1216_writereg_mask(state, AC_CONF_IND, AC_CONF_INVIQ_BIT, (u8)(bSI << 5)); +} + +static void cu1216_set_gain(struct dvb_frontend *fe, u8 bGain) +{ + struct cu1216_state *state = fe->demodulator_priv; + + // write the gain + cu1216_writereg_mask(state, AC_GAIN_IND, AC_GAIN_GNYQ_MSK, (u8)(bGain << 5)); +} + +static int cu1216_read_status(struct dvb_frontend *fe, fe_status_t *status) +{ + struct cu1216_state *state = fe->demodulator_priv; + int sync; + + *status = 0; + sync = cu1216_readreg (state, 0x11); + + if (sync & 2) + *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER; + + if (sync & 4) + *status |= FE_HAS_SYNC | FE_HAS_VITERBI; + + if (sync & 8) + { + *status |= FE_HAS_LOCK; + + return 0; + } + return -1; +} + +static int cu1216_read_errRate(struct dvb_frontend *fe) +{ + struct cu1216_state *state = fe->demodulator_priv; + + int cCkOffset = 0; + int iErrRyt; + + // read offset + cCkOffset = cu1216_readreg(state, 0x1d); + + // convert the value to long + if (cCkOffset < 0) + iErrRyt = (int)(0xFFFFFF00 | cCkOffset); + else + iErrRyt = (int)cCkOffset; + + // read DYN bit + cCkOffset = cu1216_readreg(state, 0x03); + + // calculate the error in ppm + iErrRyt *= 1000000; + iErrRyt /= 262144; + + if (!(cCkOffset & 0x08)) + iErrRyt /= 2; + + return iErrRyt; +} + +/*static int cu1216_read_quality(struct dvb_frontend *fe, u16 *quality) +{ + struct cu1216_state *state = fe->demodulator_priv; + + u8 tempval; + fe_status_t tunerStatus; + + cu1216_read_status(fe, &tunerStatus); + + if (tunerStatus == 0) { + *quality = 0; + return 0; + } + + tempval = cu1216_readreg(state, 0x18); + + if (tempval <= 5) { + *quality = 98; + return 0; + + } else if(tempval <= 10) { + *quality = 108 - 2*tempval;//88 + return 0; + } + + switch (state->params.u.qam.modulation) { + case QPSK: + case QAM_16: + if (tempval <= 110) + *quality = 60 + (110 - tempval) * 3 / 10;//0.3 + else if (tempval <= 120) + *quality = 30 + (120 - tempval) * 30 / 10; + else + *quality = (255 - tempval) * 30 / 135; + break; + case QAM_32: + if (tempval <= 72) + *quality = 60 + (72 - tempval) * 15 / 31;//0.5 + else if (tempval <= 82) + *quality = 30 + (83 - tempval) * 30 / 11; + else + *quality = (255 - tempval) * 30 / 172; + break; + default: + case QAM_64: + if (tempval <= 42) + *quality = 60 + (42- tempval) * 7 / 8;//0.875 + else if (tempval <= 52) + *quality = 30 + (52 - tempval) * 30 / 10; + else + *quality = (255-tempval)*30/203; + break; + case QAM_128: + if (tempval <= 28) + *quality = 60 + (28 - tempval) * 14 / 9;//1.5 + else if(tempval <= 34) + *quality = 30 + (34 - tempval) * 30 / 6; + else + *quality = (255 - tempval) * 30 / 221; + break; + case QAM_256: + if (tempval <= 18) + *quality = 60 + (18 - tempval) * 7 / 2;//3.5 + else if (tempval <= 22) + *quality = 30 + (22 - tempval) * 30 / 4; + else + *quality = (255 - tempval) * 30 / 233; + break; + } + + return 0; +}*/ + +static int cu1216_read_strength(struct dvb_frontend *fe, u16 *strength) +{ + struct cu1216_state *state = fe->demodulator_priv; + + u8 tempagc; + + tempagc = cu1216_readreg(state, AC_VAGC1_IND); + + if (tempagc > 0xF0) + *strength = 2; + else if (tempagc > 0xE5) + *strength = 4; + else if (tempagc < 0x6E) + *strength = 98; + else if (tempagc < 0x96) + *strength = 70 + (0x96 - tempagc) / 2 * 7 / 5; + else if (tempagc < 0xCD) + *strength = 14 + (0xCD - tempagc); + else + *strength = 2 + (0xE5 - tempagc) / 2; + + return 0; +} + +static int cu1216_read_ber(struct dvb_frontend *fe, u32 *BERvalue) +{ + struct cu1216_state *state = fe->demodulator_priv; + + u8 tempval; + + tempval = cu1216_readreg(state, 0x16); + + tempval &= 0x0f; + *BERvalue = tempval; + *BERvalue <<=8; + + tempval = cu1216_readreg(state, 0x15); + + *BERvalue += tempval; + *BERvalue <<=8; + + tempval = cu1216_readreg(state, 0x14); + + *BERvalue += tempval; + + tempval = cu1216_readreg(state, 0x10); + + switch (tempval & 0xc0) { + default: + case 0x00: // 1,00E+05 + *BERvalue *= 80; + break; + + case 0x40: // 1,00E+06 + *BERvalue *= 10; + break; + + case 0x80: // 1,00E+07 + *BERvalue /= 1; + break; + case 0xc0: // 1,00E+08 + *BERvalue /= 10; + break; + } + return 0; +} + +static int cu1216_read_snr (struct dvb_frontend *fe, u16 *SNRvalue) +{ + struct cu1216_state *state = fe->demodulator_priv; + + u8 tempagc; + + tempagc = cu1216_readreg(state, 0x18); + + *SNRvalue = tempagc; + switch (state->params.u.qam.modulation) { + case QAM_16: + *SNRvalue = 195000 / (32 * (*SNRvalue) + 138) + 100; + break; + case QAM_32: + *SNRvalue = 215000 / (40 * (*SNRvalue) + 500) + 135; + break; + default: + case QAM_64: + *SNRvalue = 210000 / (40 * (*SNRvalue) + 500) + 125; + break; + case QAM_128: + *SNRvalue = 185000 / (38 * (*SNRvalue) + 400) + 138; + break; + case QAM_256: + *SNRvalue = 180000 / (100 * (*SNRvalue) + 40) + 203; + break; + } + return 0; +} + + + +static int cu1216_read_ubk(struct dvb_frontend *fe, u32 *ubk) +{ + struct cu1216_state *state = fe->demodulator_priv; + + u8 puBytes[4]; + u32 puUBK; + + //---------------------- + // Implementation + //---------------------- + puBytes[0] = cu1216_readreg(state, AC_CPTUNCOR_IND); + puBytes[1] = cu1216_readreg(state, AC_BERLSB_IND); + puBytes[2] = cu1216_readreg(state, AC_BERMID_IND); + puBytes[3] = cu1216_readreg(state, AC_BERMSB_IND); + + + puUBK = (puBytes[3] << 24) | (puBytes[2] << 16) | (puBytes[1] << 8) | puBytes[0]; + + // mask the reset flag + puUBK &= AC_CPTUNCOR_CPTU_MSK; + + // reset the counter is needed if there are uncors + if (puUBK) { + cu1216_writereg_mask(state, AC_RSCONF_IND, AC_RSCONF_CLBUNC_BIT, 0); + cu1216_writereg_mask(state, AC_RSCONF_IND, AC_RSCONF_CLBUNC_BIT,AC_RSCONF_CLBUNC_BIT); + } + *ubk = puUBK; + + return 0; +} + +static void cu1216_clear_register(struct dvb_frontend *fe) +{ + struct cu1216_state *state = fe->demodulator_priv; + + cu1216_writereg(state, AC_CONF_IND, 0x6a); +} + +static void cu1216_check_tunertype(struct dvb_frontend *fe) +{ + struct cu1216_state *state = fe->demodulator_priv; + + type = cu1216_readreg(state, AC_IDENTITY_IND); + dprintk( verbose, MANTIS_DEBUG, 1, " Detected TunerType:0x%x", type); +} + +static int cu1216_init_none(struct dvb_frontend *fe) +{ + return 0; +} + +static int cu1216_init(struct dvb_frontend *fe) +{ + struct cu1216_state *state = fe->demodulator_priv; + + u8 bByte; + s32 lDeltaF; + u32 AC_uSysClk; + u8 puByte[3], uByte; + + u32 uSACLK,uSysClk; + u32 uTUN_IF; + u8 bFsampling,bModeDvbMcns,bBERdepth,bPolaPWM1,bPolaPWM2; + u8 bIFMax ,bIFMin; + u8 bTUNMax ,bTUNMin; + u8 bEqualType; + u8 bSwDyn ,bSwStep; + u8 bOUT_OClk1,bOUT_OClk2; + u8 bOUT_bMSBFirst1,bOUT_bParaSer1; + u8 bOUT_ModeABC1,bOUT_ParaDiv1; + u8 bOUT_bMSBFirst2; + + if(type == MK1) + { + // calculate the system frequency + AC_uSysClk = OM5734_XTALFREQ_DEF * (OM5734_PLLMFACTOR_DEF + 1); + AC_uSysClk /= (OM5734_PLLNFACTOR_DEF + 1) * (OM5734_PLLPFACTOR_DEF + 1); + + // PLL factors + cu1216_writereg(state, AC_MDIV_IND, OM5734_PLLMFACTOR_DEF); + cu1216_writereg(state, AC_NDIV_IND, OM5734_PLLNFACTOR_DEF); + cu1216_writereg(state, AC_PLL_IND, OM5734_PLLPFACTOR_DEF); + + // add by ice_Deng 2004/01/06 + cu1216_writereg(state, AC_CONTROL_IND, 0x0d); + + // enable the PLL + cu1216_writereg_mask(state, AC_PLL_IND, AC_PLL_BYPPLL_BIT, 0); + + // enable AGC2 and set PWMREF + cu1216_writereg_mask(state, AC_AGCCONF2_IND, AC_AGCCONF2_ENAGC2_BIT, AC_AGCCONF2_ENAGC2_BIT); + cu1216_writereg(state, AC_PWMREF_IND, AC_PWMREF_DEF); + + // use internal ADC + cu1216_writereg(state, AC_ADC_IND, 0x31); + cu1216_writereg(state, AC_ADC_IND, 0x31); + // use only nyquist gain + cu1216_writereg(state, AC_CLKCONF_IND, 0x0a); + // set the acquisition to +/-480ppm + cu1216_writereg(state, AC_CLKCONF_IND, 0x0a); + // POS_AGC - not in data sheet + + cu1216_writereg(state, AC_AGCCONF1_IND, 0x23); + cu1216_writereg(state, AC_AGCCONF1_IND, 0x23); + + if (AC_POLAPWM2_DEF) + cu1216_writereg_mask(state, AC_AGCCONF2_IND, AC_AGCCONF2_PPWM2_BIT, AC_AGCCONF2_PPWM2_BIT); + else + cu1216_writereg_mask(state, AC_AGCCONF2_IND, AC_AGCCONF2_PPWM2_BIT, 0); + + // set the threshold for the IF AGC + cu1216_writereg(state, AC_IFMAX_IND, AC_IFMAX_DEF); + cu1216_writereg(state, AC_IFMIN_IND, 0); //AC_IFMIN_DEF150 ; + + + // set the threshold for the TUN AGC + cu1216_writereg(state, AC_TUNMAX_IND, AC_TUNMAX_DEF); + cu1216_writereg(state, AC_TUNMIN_IND, AC_TUNMIN_DEF); + + + // set the counter of saturation to its maximun size + cu1216_writereg(state, AC_GAIN_IND, 0x23); + + // set the MPEG output clock polarity + // Added By IceDeng 12/15/2004 For Ts 188 + cu1216_writereg(state, 0x12, 0xe1); + cu1216_writereg(state, 0x12, 0xe1); + + //cyq channge star + cu1216_writereg_mask(state, AC_POLA2_IND, AC_POLA2_POCLK2_BIT, AC_POLA2_POCLK2_BIT); + + // set the position of the central coeffcient + cu1216_writereg_mask(state, AC_EQCONF1_IND, AC_EQCONF1_POSI_MSK, 0x70); + + // set the equalizer type + if (AC_EQUALTYPE_DEF) + cu1216_writereg_mask(state, AC_EQCONF1_IND, AC_EQCONF1_DFE_BIT, AC_EQUALTYPE_DEF-1); + + cu1216_writereg_mask(state, AC_EQCONF2_IND, AC_EQCONF2_SGNALGO_BIT, AC_EQCONF2_SGNALGO_BIT); + + + lDeltaF = (s32)(AC_uSysClk * 5 / 1000); + lDeltaF /= -8; + lDeltaF += (AC_TUNFI_DEF / 1000); + lDeltaF *= 2048; + lDeltaF /= (s32)(AC_uSysClk / 1000); + + cu1216_writereg(state, AC_DELTAF1_IND, (u8)lDeltaF); + cu1216_writereg(state, AC_DELTAF2_IND, (u8)(((lDeltaF>>8) & 0x03) | AC_DELTAF2_ALGOD_BIT)); + + // set the KAGC to its maximun value + cu1216_writereg_mask(state, AC_AGCCONF1_IND, AC_AGCCONF1_KAGC_MSK, 0x03); + + // set carrier algorithm parameters and SELCAR + bByte = AC_SWEEP_DEF; + bByte |= (u8)AC_CAROFFLENGTH_DEF; + bByte |= (u8)(AC_CAROFFSTEP_DEF << 2); + + cu1216_writereg(state, AC_SWEEP_IND, bByte); + + // TS interface 1 + bByte = AC_INTP_DEF; + if (AC_MSBFIRST1_DEF) + bByte |= AC_INTP_MSBFIRST_BIT; + if( AC_PARASER1_DEF) + bByte |= AC_INTP_INTSEL_BIT; + else + bByte |= AC_INTP_MSBFIRST_BIT; // set to 1 MSB if parallel + + if (AC_MODEAB1_DEF) { + bByte |= AC_INTP_PARMOD_BIT; + bByte |= (AC_PARADIV1_DEF << 4); + } + cu1216_writereg(state, AC_INTP_IND, bByte); + cu1216_writereg_mask(state, AC_POLA2_IND, AC_POLA2_MSBFIRST2_BIT, AC_POLA2_MSBFIRST2_BIT); + + // set the BER depth + cu1216_writereg_mask(state, AC_RSCONF_IND, AC_RSCONF_PVBER_MSK, (AC_BERDEPTH_DEF<< 6)); + } + else + { + // calculate the system frequency + uSysClk = OM5734_XTALFREQ_DEF * (OM5734_PLLMFACTOR_DEF + 1); + uSysClk /= (OM5734_PLLNFACTOR_DEF + 1) * (OM5734_PLLPFACTOR_DEF + 1); + + // Calculate the sampling clock + bFsampling=1; + if(bFsampling) + { + // high sampling clock + uSACLK = uSysClk; + } + else + { + // low sampling clock + uSACLK = uSysClk/2; + } + // read the PLL M,N,P values + puByte[0] = cu1216_readreg( state,AC_MDIV_IND ); + puByte[1] = cu1216_readreg( state,AC_NDIV_IND ); + + uByte = cu1216_readreg( state,AC_CONF_IND ); + + // change the PLL M,N,P values and FSAMPLING only if different + if((puByte[0] != OM5734_PLLMFACTOR_DEF) || + ((puByte[1] & TDA10023_PLL2_PDIV_MSK) != OM5734_PLLNFACTOR_DEF) || + (((puByte[1] & TDA10023_PLL2_NDIV_MSK)>>6) != OM5734_PLLPFACTOR_DEF) || + (((uByte & TDA10023_GPR_FSAMPLING_BIT) >> 5) != bFsampling) ) + { + u8 uPLL3; + + // disable the PLL + uPLL3 = cu1216_readreg( state,AC_PLL_IND ) ; + + uPLL3 |= (TDA10023_PLL3_BYPPLL_BIT | TDA10023_PLL3_PDPLL_BIT); + + cu1216_writereg( state,AC_PLL_IND, uPLL3); + // !!!! NOTE !!!! : When the PLL is disable, TDA10023 registers can't be read + // Therefore, SY_Read and SY_WriteBit functions must not be called + + // PLL factors + puByte[0] = OM5734_PLLMFACTOR_DEF; + puByte[1] = OM5734_PLLNFACTOR_DEF & 0x3F; + puByte[1] |= OM5734_PLLPFACTOR_DEF << 6; + + // write the PLL registers with PLL bypassed + cu1216_writereg( state,AC_MDIV_IND, puByte[0]); + cu1216_writereg( state,AC_NDIV_IND, puByte[1]); + + // Set FSAMPLING + if(bFsampling) + { + uByte = TDA10023_GPR_FSAMPLING_BIT | TDA10023_GPR_CLBS2_BIT | TDA10023_GPR_CLBS_BIT; + cu1216_writereg( state,AC_CONF_IND, uByte); + + } + else + { + + uByte = TDA10023_GPR_CLBS2_BIT | TDA10023_GPR_CLBS_BIT; + cu1216_writereg( state,AC_CONF_IND, uByte); + + } + + // enable the PLL + uPLL3 &= ~(TDA10023_PLL3_BYPPLL_BIT | TDA10023_PLL3_PDPLL_BIT); + cu1216_writereg(state,AC_PLL_IND, uPLL3); + + } + + // Set DVB/MCNS mode + bModeDvbMcns=0; + bBERdepth=2; + if (bModeDvbMcns) + { + // MCNS mode + cu1216_writereg_mask( state,AC_RESET_IND,TDA10023_RESET_DVBMCNS_BIT, + TDA10023_RESET_DVBMCNS_BIT); + + // set the BER depth + cu1216_writereg_mask( state,TDA10023_RSCFG_IND, 0x0c, bBERdepth << 2); + } + else + { + // DVB mode + cu1216_writereg_mask( state,AC_RESET_IND,TDA10023_RESET_DVBMCNS_BIT, 0); + + // set the BER depth + cu1216_writereg_mask( state,AC_RSCONF_IND, 0xc0, bBERdepth << 6); + + } + + // set GAIN1 bit to 0 + uByte = 0x82; + cu1216_writereg( state,AC_GAIN_IND, uByte); + + // set the acquisition to +/-480ppm + cu1216_writereg_mask( state,AC_CLKCONF_IND, TDA10023_CLKCONF_DYN_BIT,TDA10023_CLKCONF_DYN_BIT); + + // TRIAGC, POSAGC, enable AGCIF +#ifdef _MULTIFE_CU1216 + cu1216_writereg_mask( state,AC_AGCCONF2_IND, + TDA10023_AGCCONF2_TRIAGC_BIT | TDA10023_AGCCONF2_POSAGC_BIT | TDA10023_AGCCONF2_ENAGCIF_BIT, + 0 | TDA10023_AGCCONF2_POSAGC_BIT) ; +#else + cu1216_writereg_mask( state,AC_AGCCONF2_IND, + TDA10023_AGCCONF2_TRIAGC_BIT | TDA10023_AGCCONF2_POSAGC_BIT | TDA10023_AGCCONF2_ENAGCIF_BIT, + 0 | TDA10023_AGCCONF2_POSAGC_BIT | 0); + +#endif + // set the AGCREF + uByte = 80; + cu1216_writereg( state,AC_AGCREF_IND, uByte); + + + // set SACLK_OFF + cu1216_writereg_mask( state,0x1e,TDA10023_CONTROL_OLDBYTECLK_BIT ,TDA10023_CONTROL_OLDBYTECLK_BIT ); + + // program CS depending on SACLK and set GAINADC + uByte = 0xc8; + + cu1216_writereg( state,AC_ADC_IND, uByte); + + // set the polarity of the PWM for the AGC + bPolaPWM1=0; + if (bPolaPWM1) + { + cu1216_writereg_mask( state,AC_AGCCONF2_IND, TDA10023_AGCCONF2_PPWMTUN_BIT, TDA10023_AGCCONF2_PPWMTUN_BIT); + } + else + { + cu1216_writereg_mask( state,AC_AGCCONF2_IND, TDA10023_AGCCONF2_PPWMTUN_BIT, 0); + } + bPolaPWM2=0; + if (bPolaPWM2) + { + cu1216_writereg_mask( state,AC_AGCCONF2_IND, TDA10023_AGCCONF2_PPWMIF_BIT, TDA10023_AGCCONF2_PPWMIF_BIT); + } + else + { + cu1216_writereg_mask( state,AC_AGCCONF2_IND, TDA10023_AGCCONF2_PPWMIF_BIT, 0); + } + // set the threshold for the IF AGC + bIFMax=255; + bIFMin=0; + puByte[0] = bIFMax; + puByte[1] = bIFMin; + + cu1216_writereg( state,AC_IFMAX_IND, puByte[0]); + cu1216_writereg( state,AC_IFMIN_IND , puByte[1]); + + // set the threshold for the TUN AGC + bTUNMax=255; + bTUNMin=0; + puByte[0] = bTUNMax; + puByte[1] = bTUNMin; + + cu1216_writereg(state, AC_TUNMAX_IND , puByte[0]); + cu1216_writereg(state, AC_TUNMIN_IND , puByte[1]); + + // configure the equalizer + bEqualType=2; + if(bEqualType == 0) + { + // disable the equalizer + uByte = 0x70; + } + else + { + // enable the equalizer and set the DFE bit + uByte = 0x70 | TDA10023_EQCONF1_ENADAPT_BIT | + TDA10023_EQCONF1_ENEQUAL_BIT |(bEqualType-1); + } + cu1216_writereg( state,AC_EQCONF1_IND , uByte); + + + cu1216_writereg_mask( state,AC_EQCONF2_IND, + TDA10023_EQCONF2_SGNALGO_BIT | TDA10023_EQCONF2_STEPALGO_BIT, + TDA10023_EQCONF2_SGNALGO_BIT | TDA10023_EQCONF2_STEPALGO_BIT); + + // set ALGOD and deltaF + uTUN_IF=36130000; + + if(bFsampling) + { + // FSAMPLING = 1 - high sampling clock + // SACLK = Sysclk (SACLK max = 72MHz) + lDeltaF = (long)(uTUN_IF/1000); + lDeltaF *= 32768; // 32768 = 2^20/32 + lDeltaF += (long)(uSysClk/500); + lDeltaF /= (long)(uSysClk/1000); + lDeltaF -= 53248; // 53248 = (2^20/32) * 13/8 + } + else + { + // FSAMPLING = 0 - low sampling clock + // SACLK = Sysclk/2 (SACLK max = 36MHz) + lDeltaF = (long)(uTUN_IF/1000); + lDeltaF *= 32768; // 32768 = 2^20/32 + lDeltaF += (long)(uSysClk/1000); + lDeltaF /= (long)(uSysClk/2000); + lDeltaF -= 40960; // 53248 = (2^20/32) * 5/4 + } + + puByte[0] = (u8)lDeltaF; + puByte[1] = (u8)(((lDeltaF>>8) & 0x7F) | TDA10023_DELTAF_MSB_ALGOD_BIT); + + cu1216_writereg( state,AC_DELTAF1_IND , puByte[0]); + cu1216_writereg( state,AC_DELTAF2_IND , puByte[1]); + + // set the KAGCIF and KAGCTUN to acquisition mode + uByte = 0x93;//0x93 cyqagc + cu1216_writereg( state,AC_AGCCONF1_IND , uByte); + + + // set carrier algorithm parameters + bSwDyn=0;//7 + bSwStep=1; + uByte = 0x82; + uByte |= bSwDyn << 4; + uByte |= bSwStep << 2; + cu1216_writereg( state,AC_SWEEP_IND , uByte); + + // set the MPEG output clock polarity + bOUT_OClk1=1; + bOUT_OClk2=1; + if(bOUT_OClk1) + { + cu1216_writereg_mask( state, + AC_POLA1_IND, TDA10023_INTP1_POCLKP_BIT, TDA10023_INTP1_POCLKP_BIT); + } + else + { + cu1216_writereg_mask(state, + AC_POLA1_IND, TDA10023_INTP1_POCLKP_BIT, 0); + } + if(bOUT_OClk2) + { + cu1216_writereg_mask(state, + AC_POLA2_IND, TDA10023_INTS1_POCLKS_BIT, TDA10023_INTS1_POCLKS_BIT); + } + else + { + cu1216_writereg_mask(state, + AC_POLA2_IND, TDA10023_INTS1_POCLKS_BIT, 0); + } + + // TS interface 1 + uByte = 0; + bOUT_bMSBFirst1=0; + bOUT_bParaSer1=0; + if(bOUT_bMSBFirst1) + uByte |= TDA10023_INTP2_MSBFIRSTP_BIT; + if(bOUT_bParaSer1) + { + // SERIAL + uByte |= 0x03; + } + else + { + // PARALLEL + // set to 1 MSB if parallel + uByte |= TDA10023_INTP2_MSBFIRSTP_BIT; + bOUT_ModeABC1=0; + bOUT_ParaDiv1=0; + if(bOUT_ModeABC1 == 0) + { + // PARALLEL mode A + uByte |= 0x00; + } + else if(bOUT_ModeABC1 == 1) + { + // PARALLEL mode B + uByte |= 0x01; + uByte |= bOUT_ParaDiv1 << 4; + } + else //if(bOUT_ModeABC1 == 2) + { + // PARALLEL mode C + uByte |= 0x02; + } + } + cu1216_writereg(state, 0x20 , uByte); + + + + // TS interface 2 + bOUT_bMSBFirst2=0; + if(bOUT_bMSBFirst2) + { + cu1216_writereg_mask( state,AC_CONTROL_IND, TDA10023_INTPS_MSBFIRSTS_BIT, + TDA10023_INTPS_MSBFIRSTS_BIT); + } + else + { + cu1216_writereg_mask( state,AC_CONTROL_IND, TDA10023_INTPS_MSBFIRSTS_BIT, 0); + } + // disable the tri state of the outputs + cu1216_writereg_mask( state,AC_CONTROL_IND, TDA10023_INTPS_TRIP_BIT | TDA10023_INTPS_TRIS_BIT, 0); + + + // Soft reset + cu1216_writereg_mask(state, 0x00, TDA10023_GPR_CLBS2_BIT | TDA10023_GPR_CLBS_BIT, TDA10023_GPR_CLBS2_BIT | 0); + } + return 0; +} + +static void delay_ms_interruptible(u32 ms) +{ + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(HZ * ms / 100); +} + +static void delay_us_interruptible(u32 us) +{ + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(HZ * us / 10000); +} + +static int tda10023_set_tuner(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params) +{ + struct cu1216_state *state = fe->demodulator_priv; + + u32 uFreqPll,uRfProg; + u8 pTunerReg[6]; + struct i2c_msg msg = { + .addr = 0xc0 >> 1, + .flags = 0, + .buf = pTunerReg, + .len = 4 + }; + + dprintk(verbose, MANTIS_ERROR, 1, "Freq = %d", params->frequency); + + cu1216_writereg(state, 0x02, 0x93); + // call the tuner function with the tuner IF + + // calculate N0-N14 + uFreqPll = params->frequency;//*1000; + uFreqPll +=36130000; + uFreqPll += 62500/2; + uRfProg = uFreqPll; + uFreqPll /= 62500; + + // real frequency programmed + // uRfProg = uFreqPll * uPllStep; + //------------- + // byte 0 and 1 + //------------- + // divider ratio + pTunerReg[0] = (u8)(uFreqPll >> 8); + pTunerReg[1] = (u8)uFreqPll; + //------- + // byte 2 + //------- + // pTunerReg[2] &= 0xF9; + pTunerReg[2] = 0xCE; + pTunerReg[2] &= 0xF8; + pTunerReg[2] |= 0x06; + //------- + // byte 3 + //------- + // pTunerReg[3] &= 0xF8; + pTunerReg[3] = 0x00; + + if (uRfProg < (160000000 + 36125000)) + pTunerReg[3] |= 0x01; + else if (uRfProg > (446000000 + 36125000)) // high band + pTunerReg[3] |= 0x04; + else // mid band + pTunerReg[3] |= 0x02; + //------- + // byte 4 = byte 2 with T2T1T0 = 011 for AB Byte Xfer + //------- + pTunerReg[4] = pTunerReg[2] & 0xC7; // mask first + pTunerReg[4] |= 0x18; // T2T1T0 = 011 + + //------- + // byte 5 = AB byte + //------- + pTunerReg[5] = 0x00 | 0 << 7 | 2 << 4; + + // write in the tuner + // first, CB + AB bytes + tda10023_writereg(state, pTunerReg[4], pTunerReg[5]); + + // then all the other bytes, DB1, DB2, CB and BB + if (i2c_transfer(state->i2c, &msg, 1) < 0) { + printk("%s tuner not ack!\n", __FUNCTION__); + return -EIO; + } + tda10023_writereg(state, pTunerReg[4], pTunerReg[5]); + + msleep(100); + return 0; + +} + +static int cu1216_set_parameters(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) +{ + struct cu1216_state *state = fe->demodulator_priv; + + u8 i; + u8 QamSize = 0; + u32 ErrRate[3]; + fe_status_t value; + int status = -EINVAL; + u8 li_Iq, li_oldIq = 0, uc_Gain, uc_oldGain = 0; + + /*printk("[%s]:frequency = %d , symbol = %d , qam = %d .\n", + __func__, + params->frequency , params->u.qam.symbol_rate, + params->u.qam.modulation);*/ + + //get tuner type for mk1 mk3 + cu1216_check_tunertype(fe); + if(type == MK1) + { + + dprintk( verbose, MANTIS_DEBUG, 1, " MK1"); + switch (params->u.qam.modulation) { + case QPSK : + QamSize = 0; + break; + case QAM_16 : + QamSize = 1; + break; + case QAM_32 : + QamSize = 2; + break; + case QAM_64 : + QamSize = 3; + break; + case QAM_128: + QamSize = 4; + break; + case QAM_256: + QamSize = 5; + break; + default : + printk("[cu1216_set_parameters]:QAM set error!\n"); + break; + } + + if (li_oldIq >= 2) + li_oldIq = 0; + + //reset tuner + //state->config->fe_reset(fe); + + //To clear the Registers in TDA10021HT + cu1216_clear_register(fe); + + //Write Frequency into tuner + lock_tuner(state); + state->config->pll_set(fe, params); + unlock_tuner(state); + + //mdelay(20); + delay_ms_interruptible(10); + + //Second step to init the cu1216ht's registers + cu1216_init(fe); + + //Write Symborate + cu1216_set_symbolRate(fe, params->u.qam.symbol_rate / 1000); + + //Write QAM + cu1216_set_QAM(fe, QamSize); + + for (i = li_oldIq; i < li_oldIq + 2; i++) { + li_Iq = i % 2; + + for (uc_Gain = 1; uc_Gain < 4; uc_Gain++) { + cu1216_set_IQ(fe, li_Iq); + + cu1216_set_gain(fe, uc_Gain); + + //udelay(50); + delay_us_interruptible(5); + + if (cu1216_read_status(fe, &value) == 0) { + + li_oldIq = li_Iq; + uc_oldGain = uc_Gain; + ErrRate[0] = cu1216_read_errRate(fe); + + if (uc_Gain < 3) { + cu1216_set_gain(fe, uc_Gain+1); + //udelay(50); + delay_us_interruptible(5); + ErrRate[1] = cu1216_read_errRate(fe); + + if (ErrRate[0] > ErrRate[1]) { + cu1216_set_gain(fe , uc_Gain); + //udelay(50); + delay_us_interruptible(5); + + } else { + uc_oldGain = uc_Gain + 1; + uc_Gain = uc_Gain + 1; + + if (uc_Gain < 3) { + cu1216_set_gain(fe, uc_Gain + 1); + + //udelay(50); + delay_us_interruptible(5); + ErrRate[2] = cu1216_read_errRate(fe); + + if (ErrRate[1] > ErrRate[2]) { + cu1216_set_gain(fe , uc_oldGain); + + //udelay(50); + delay_us_interruptible(5); + } else { + uc_oldGain = uc_Gain + 1; + } + } + } + } + goto ret; + } + } + } + + status = -1; + }else{ + dprintk( verbose, MANTIS_DEBUG, 1, " MK3"); + switch(params->u.qam.modulation) + { + //case QPSK : QamSize = 0; break; + case QAM_16 : QamSize = 1; break; + case QAM_32 : QamSize = 2; break; + case QAM_64 : QamSize = 3; break; + case QAM_128: QamSize = 4; break; + case QAM_256: QamSize = 5; break; + default : QamSize = 3; break; + } + //reset tuner + state->config->fe_reset(fe); + + //Write Frequency into tuner + lock_tuner(state); + tda10023_set_tuner(fe, params); + unlock_tuner(state); + + //Second step to init the cu1216ht's registers + cu1216_init(fe); + + //Write Symborate + cu1216_set_symbolRate(fe, params->u.qam.symbol_rate / 1000); + + //Write QAM + cu1216_set_QAM(fe, QamSize); + + //cu1216_wait(50); + delay_ms_interruptible(50); + cu1216_writereg(state, AC_AGCCONF1_IND, 0x9B);//0x9B hick track mode + + //AC_WriteSI( 2); + cu1216_writereg_mask(state, AC_CARCONF_IND, + TDA10023_CARCONF_AUTOINVIQ_BIT | TDA10023_CARCONF_INVIQ_BIT, + (u8)(2<<5)); + + //Soft reset + cu1216_writereg_mask(state,AC_CONF_IND, + TDA10023_GPR_CLBS2_BIT | TDA10023_GPR_CLBS_BIT, + TDA10023_GPR_CLBS2_BIT | 0); + + return 0 ; + } +ret: + state->params = *params; + return status ; +} + +static int cu1216_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) +{ + struct cu1216_state *state = fe->demodulator_priv; + int sync; + s8 afc = 0; + + sync = cu1216_readreg(state, 0x11); + afc = cu1216_readreg(state, 0x19); + if (verbose) { + /* AFC only valid when carrier has been recovered */ + printk(sync & 2 ? "DVB: TDA10021(%d): AFC (%d) %dHz\n" : + "DVB: TDA10021(%d): [AFC (%d) %dHz]\n", + state->frontend.dvb->num, afc, + - ((s32)p->u.qam.symbol_rate * afc) >> 10); + } + + p->inversion = HAS_INVERSION(state->reg0) ? INVERSION_ON : INVERSION_OFF; + p->u.qam.modulation = ((state->reg0 >> 2) & 7) + QAM_16; + + p->u.qam.fec_inner = FEC_NONE; + p->frequency = ((p->frequency + 31250) / 62500) * 62500; + + if (sync & 2) + p->frequency -= ((s32)p->u.qam.symbol_rate * afc) >> 10; + + return 0; +} + + +static int cu1216_sleep(struct dvb_frontend *fe) +{ + struct cu1216_state *state = fe->demodulator_priv; + + cu1216_writereg (state, 0x1b, 0x02); /* pdown ADC */ + cu1216_writereg (state, 0x00, 0x80); /* standby */ + + return 0; +} + +static void cu1216_release(struct dvb_frontend *fe) +{ + struct cu1216_state *state = fe->demodulator_priv; + kfree(state); +} + +static struct dvb_frontend_ops cu1216_ops; + +struct dvb_frontend *cu1216_attach(const struct cu1216_config *config, + struct i2c_adapter *i2c) +{ + struct cu1216_state *state = NULL; + + /* allocate memory for the internal state */ + state = kmalloc(sizeof (struct cu1216_state), GFP_KERNEL); + if (state == NULL) + goto error; + + /* setup the state */ + state->config = config; + state->i2c = i2c; + memcpy(&state->ops, &cu1216_ops, sizeof (struct dvb_frontend_ops)); + + /* check if the demod is there */ + if ((cu1216_readreg(state, 0x1a) & 0xf0) != 0x70) //reg 0x1a == 0x7c + goto error; + + /* create dvb_frontend */ + state->frontend.ops = state->ops; + state->frontend.demodulator_priv = state; + return &state->frontend; + +error: + kfree(state); + return NULL; +} + +static struct dvb_frontend_ops cu1216_ops = { + + .info = { + .name = "Philips CU1216 DVB-C", + .type = FE_QAM, + .frequency_stepsize = 62500, + .frequency_min = 51000000, + .frequency_max = 858000000, + .symbol_rate_min = (XIN / 2) / 64, /* SACLK/64 == (XIN/2)/64 */ + .symbol_rate_max = (XIN / 2) / 4, /* SACLK/4 */ + .caps = 0x400 | //FE_CAN_QAM_4 + FE_CAN_QAM_16 | + FE_CAN_QAM_32 | + FE_CAN_QAM_64 | + FE_CAN_QAM_128 | + FE_CAN_QAM_256 | + FE_CAN_FEC_AUTO + }, + + .release = cu1216_release, + .init = cu1216_init_none, + .sleep = cu1216_sleep, + .set_frontend = cu1216_set_parameters, + .get_frontend = cu1216_get_frontend, + .read_status = cu1216_read_status, + .read_ber = cu1216_read_ber, + .read_signal_strength = cu1216_read_strength, + .read_snr = cu1216_read_snr, + .read_ucblocks = cu1216_read_ubk, +}; + + +MODULE_DESCRIPTION("Philips CU1216 DVB-C demodulator driver"); +MODULE_AUTHOR("Ralph Metzler, Holger Waechtler, Markus Schulz"); +MODULE_LICENSE("GPL"); + +EXPORT_SYMBOL(cu1216_attach); diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/frontends/cu1216.h kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/cu1216.h --- kernel-2.6.24.4-orig/drivers/media/dvb/frontends/cu1216.h 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/cu1216.h 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,58 @@ +/* + CU-1216 driver for the Mantis bridge based cards + + Copyright (C) 2005 Twinhan Technology Co. Ltd + based on the TDA 10021 driver + + Copyright (C) 1999 Convergence Integrated Media GmbH + Copyright (C) 2004 Markus Schulz + + Copyright (C) 2005, 2006 Manu Abraham (abraham.manu@gmail.com) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#ifndef __CU1216_H +#define __CU1216_H + +#include +struct cu1216_state { + struct i2c_adapter *i2c; + struct dvb_frontend_ops ops; + + //configuration settings + const struct cu1216_config *config; + struct dvb_frontend frontend; + + u8 pwm; + u8 reg0; + + struct dvb_frontend_parameters params; +}; + +struct cu1216_config { + /* the demodulator's i2c address */ + u8 demod_address; + + /* PLL maintenance */ + int (*pll_init)(struct dvb_frontend *fe); + int (*pll_set)(struct dvb_frontend *fe, struct dvb_frontend_parameters *params); + int (*fe_reset)(struct dvb_frontend *fe); +}; + +extern struct dvb_frontend *cu1216_attach(const struct cu1216_config *config, struct i2c_adapter *i2c); + + +#endif //__MANTIS_CU1216_H diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/frontends/cu1216_regs.h kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/cu1216_regs.h --- kernel-2.6.24.4-orig/drivers/media/dvb/frontends/cu1216_regs.h 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/cu1216_regs.h 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,440 @@ +#ifndef __CU1216_REGS_H +#define __CU1216_REGS_H + +#define XIN 57840000UL + +#define DISABLE_INVERSION(reg0) do { reg0 |= 0x20; } while (0) +#define ENABLE_INVERSION(reg0) do { reg0 &= ~0x20; } while (0) +#define HAS_INVERSION(reg0) (!(reg0 & 0x20)) + +#define FIN (XIN >> 4) + +#define MK1 0x7c +#define MK3 0x7d +//////////////////// +#define C_1216_CHIP_ADDRESS 0x18 +#define C_1216_TUNER_ADDRESS 0xc0 + + +#define OM5734_XTALFREQ_DEF 28920000 +#define OM5734_PLLMFACTOR_DEF 0x07 +#define OM5734_PLLNFACTOR_DEF 0x00 +#define OM5734_PLLPFACTOR_DEF 0x03 + +#define CU1216_PLLMFACTOR_DVB_DEF 0x07 // ins Dirty was 0x07 +#define CU1216_PLLNFACTOR_DVB_DEF 0x00 //ins Dirty was 0x00 +#define CU1216_PLLPFACTOR_DVB_DEF 0x03 //ins Dirty was 0x03 +#define CU1216_XTALL_FREQ_28 28920000 + +#define AC_POLAPWM1_DEF 0 +#define AC_POLAPWM2_DEF 0 +#define AC_IFMAX_DEF 255 +#define OM5735_IFMIN_DEF 64 +#define OM5734_IFMIN_DEF 88 +#define AC_TUNMAX_DEF 255 +#define AC_TUNMIN_DEF 0 +#define AC_IFMIN_DEF150 150 + + +#define AC_EQUALTYPE_DEF 2 +#define AC_BERDEPTH_DEF 2 +#define AC_CAROFFSTEP_DEF 1 +#define AC_CAROFFLENGTH_DEF 1 +#define AC_CARRANGE_DEF 1 +#define AC_DISAFC_DEF 0 + +#define AC_IQSWAPPED_DEF 1 +#define AC_TUNID_DEF 0 +#define AC_TUNREADENA_DEF 0 +#define AC_TUNFI_DEF 36125000 + +#define AC_POCLK1_DEF 1 +#define AC_PARASER1_DEF 0 +#define AC_MSBFIRST1_DEF 0 +#define AC_MODEAB1_DEF 0 +#define AC_PARADIV1_DEF 0 +#define AC_POCLK2_DEF 1 +#define AC_PARASER2_DEF 0 + +#define OM5734_DEF 0 +#define OM5735_DEF 1 +#define CUSTOM_DEF 2 + +/* +Definition the index of regiester +********************************************************************************* +*/ +#define AC_CONF_IND 0x00 +#define AC_AGCREF_IND 0x01 +#define AC_AGCCONF1_IND 0x02 +#define AC_CLKCONF_IND 0x03 +#define AC_CARCONF_IND 0x04 +#define AC_LOCKTHR_IND 0x05 +#define AC_EQCONF1_IND 0x06 +#define AC_EQSTEP_IND 0X07 +#define AC_MSETH_IND 0x08 +#define AC_AREF_IND 0x09 +#define AC_BDRLSB_IND 0x0A +#define AC_BDRMID_IND 0x0B +#define AC_BDRMSB_IND 0x0C +#define AC_BDRINV_IND 0x0D +#define AC_GAIN_IND 0x0E +#define AC_TEST_IND 0x0F +#define AC_RSCONF_IND 0x10 +#define AC_SYNC_IND 0x11 +#define AC_POLA1_IND 0x12 +#define AC_CPTUNCOR_IND 0x13 +#define AC_BERLSB_IND 0x14 +#define AC_BERMID_IND 0x15 +#define AC_BERMSB_IND 0x16 +#define AC_VAGC1_IND 0x17 +#define AC_MSE_IND 0x18 +#define AC_VAFC_IND 0x19 +#define AC_IDENTITY_IND 0x1A +#define AC_ADC_IND 0x1B +#define AC_EQCONF2_IND 0x1C +#define AC_CKOFFSET_IND 0x1D + +//#define AC_CONTROL +#define AC_RESET_IND 0x1f + +#define AC_INTP_IND 0x20 +#define AC_SATNYQ_IND 0x21 +#define AC_SATADC_IND 0x22 +#define AC_HALFADC_IND 0x23 +#define AC_SATDEC1_IND 0x24 +#define AC_SATDEC2_IND 0x25 +#define AC_SATDEC3_IND 0x26 +#define AC_SATAAF_IND 0x27 +#define AC_MDIV_IND 0x28 +#define AC_NDIV_IND 0x29 +#define AC_PLL_IND 0x2A +#define AC_POLA2_IND 0x2B +#define AC_CONTROL_IND 0x2C +#define AC_SWEEP_IND 0x2D +#define AC_AGCCONF2_IND 0x2E +#define AC_VAGC2_IND 0x2F +#define AC_SATTHR_IND 0x30 +#define AC_HALFTHR_IND 0x31 +#define AC_ITSEL_IND 0x32 +#define AC_ITSTAT_IND 0x33 +#define AC_PWMREF_IND 0x34 +#define AC_TUNMAX_IND 0x35 +#define AC_TUNMIN_IND 0x36 +#define AC_DELTAF1_IND 0x37 +#define AC_DELTAF2_IND 0x38 +#define AC_CONSTI_IND 0x39 +#define AC_CONSTQ_IND 0x3A +#define AC_IFMAX_IND 0x3B +#define AC_IFMIN_IND 0x3C + +#define AC_REQCO_IND 0x40 +#define AC_REQCO_CENTRALCOEF_IND 0x50 + +#define AC_IEQCO_IND 0x80 +#define AC_IEQCO_CENTRALCOEF_IND 0x90 +/****add *****/ +#define TDA10023_REQCO_IND 0x40 +#define TDA10023_REQCO_CENTRALCOEF_IND 0x50 + +#define TDA10023_CPT_TSP_UNCOR1_IND 0x74 +#define TDA10023_CPT_TSP_UNCOR2_IND 0x75 +#define TDA10023_CPT_TSP_UNCOR3_IND 0x76 +#define TDA10023_CPT_TSP_UNCOR4_IND 0x77 +#define TDA10023_CPT_TSP_COR1_IND 0x78 +#define TDA10023_CPT_TSP_COR2_IND 0x79 +#define TDA10023_CPT_TSP_COR3_IND 0x7A +#define TDA10023_CPT_TSP_COR4_IND 0x7B +#define TDA10023_CPT_TSP_OK1_IND 0x7C +#define TDA10023_CPT_TSP_OK2_IND 0x7D +#define TDA10023_CPT_TSP_OK3_IND 0x7E +#define TDA10023_CPT_TSP_OK4_IND 0x7F + +#define TDA10023_IEQCO_IND 0x80 +#define TDA10023_IEQCO_CENTRALCOEF_IND 0x90 + +#define TDA10023_AGCREFNYQ_IND 0xB4 +#define TDA10023_ERAGC_THD_IND 0xB5 +#define TDA10023_ERAGCNYQ_THD_IND 0xB6 +#define TDA10023_SCIN_THDL_IND 0xB7 +#define TDA10023_SCIN_THDH_IND 0xB8 +#define TDA10023_SCIN_CPTL_IND 0xB9 +#define TDA10023_SCIN_CPTH_IND 0xBA +#define TDA10023_SCIN_CPT_IND 0xBB +#define TDA10023_SCIN_NBTSAT_IND 0xBC +#define TDA10023_SATDEC0_IND 0xBD +#define TDA10023_INVQ_AGC_IND 0xBE +#define TDA10023_BW_AGC_IND 0xBF +#define TDA10023_XTAL_PLL4_IND 0xC0 +#define TDA10023_PLL5_IND 0xC1 +#define TDA10023_CLBSTIM_I2CSWTCH_IND 0xC2 +#define TDA10023_TIMING_SCAN_IND 0xC3 +#define TDA10023_TIMING_PPM_IND 0xC4 +#define TDA10023_TIMING_PARA1_IND 0xC5 +#define TDA10023_TIMING_PARA2_IND 0xC6 +#define TDA10023_TIMING_STATUS_IND 0xC7 +#define TDA10023_CPT_TRANS_IND 0xC8 +#define TDA10023_PERCENTAGE_IND 0xC9 +#define TDA10023_ERTIM_THD_IND 0xCA +#define TDA10023_DSP_IND 0xCB +#define TDA10023_POWER1_IND 0xCC +#define TDA10023_POWER2_IND 0xCD +#define TDA10023_POWER3_IND 0xCE + +#define TDA10023_CTRL1_IND 0xD0 +#define TDA10023_CTRL2_IND 0xD1 +#define TDA10023_TRELDAT_IND 0xD2 +#define TDA10023_TRELCOR_IND 0xD3 +#define TDA10023_FECSYNC_IND 0xD4 +#define TDA10023_DRNDSD1_IND 0xD5 +#define TDA10023_DRNDSD2_IND 0xD6 +#define TDA10023_DRNDSD3_IND 0xD7 +#define TDA10023_CPT_RSB_UNCOR1_IND 0xD8 +#define TDA10023_CPT_RSB_UNCOR2_IND 0xD9 +#define TDA10023_CPT_RSB_UNCOR3_IND 0xDA +#define TDA10023_CPT_RSB_UNCOR4_IND 0xDB +#define TDA10023_FECRSYNC_IND 0xDC +#define TDA10023_DEINTRLV_IND 0xDD + +#define TDA10023_STATUS_MCNS_IND 0xE0 +#define TDA10023_VITERBI_LOCK_IND 0xE1 +#define TDA10023_RSUNCORLO_IND 0xE2 +#define TDA10023_RSUNCORHI_IND 0xE3 +#define TDA10023_RSBERLO_IND 0xE4 +#define TDA10023_RSBERHI_IND 0xE5 +#define TDA10023_RSCFG_IND 0xE6 +#define TDA10023_CPT_RSB_COR1_IND 0xE7 +#define TDA10023_CPT_RSB_COR2_IND 0xE8 +#define TDA10023_CPT_RSB_COR3_IND 0xE9 +#define TDA10023_CPT_RSB_COR4_IND 0xEA +#define TDA10023_CPT_RSB_OK1_IND 0xEB +#define TDA10023_CPT_RSB_OK2_IND 0xEC +#define TDA10023_CPT_RSB_OK3_IND 0xED +#define TDA10023_CPT_RSB_OK4_IND 0xEE + +#define TDA10023_EMPTY_FECMCNS_IND 0xFA +#define TDA10023_EMPTY1_TOP_IND 0xFB +#define TDA10023_EMPTY2_TOP_IND 0xFC +#define TDA10023_EMPTY_DEMOD_IND 0xFD +#define TDA10023_EMPTY_FEC_DVB_IND 0xFE + + + +/*********************/ +/* DEFAULT VALUES */ +/*********************/ +#define AC_ADC_SW_DEF 0x30 +#define AC_CARCONFHIGHSR_DEF 0x02 +#define AC_CARCONFLOWSR_DEF 0x0A +#define AC_CARCONFVERYLOWSR_DEF 0x05 +#define AC_CARCONFALGO_DEF 0x0C +#define AC_PWMREF_DEF 0x80 +#define AC_INTP_DEF 0x00 +#define AC_SWEEP_DEF 0x80 + + +/*********************/ +/* DEFINE VALUES */ +/*********************/ +#define AC_NOSI_VAL 0 +#define AC_YESSI_VAL 1 +#define AC_AUTOSI_VAL 2 + +#define AC_PHILIPS_VAL 0 +#define AC_PHILIPSLHI_VAL 1 +#define AC_SONY_VAL 2 +#define AC_NOTUNER_VAL 3 + +#define AC_16QAM_VAL 0 +#define AC_32QAM_VAL 1 +#define AC_64QAM_VAL 2 +#define AC_128QAM_VAL 3 +#define AC_256QAM_VAL 4 +#define AC_4QAM_VAL 5 + +//#define AC_AUTOQAM_VAL 6 the philips value +#define AC_AUTOQAM_VAL 2 +#define AC_FREF_VAL62500 62500L +#define AC_FREF_VAL 78125 + +#define AC_PHILIPSLOW_VAL 0xA1 +#define AC_PHILIPSMID_VAL 0x92 +#define AC_PHILIPSHIGH_VAL 0x34 + +#define AC_PHILIPSLHILOW_VAL 0x06 +#define AC_PHILIPSLHIMID_VAL 0x05 +#define AC_PHILIPSLHIHIGH_VAL 0x03 + +#define AC_VHF1_SONY_VAL 0x01 +#define AC_VHF3_SONY_VAL 0x02 +#define AC_UHF_SONY_VAL 0x04 + +#define AC_BER_DEPTH5_VAL 0x00 +#define AC_BER_DEPTH6_VAL 0x40 +#define AC_BER_DEPTH7_VAL 0x80 +#define AC_BER_DEPTH8_VAL 0xC0 + +#define AC_VERYFASTAGCCONV_VAL 0 +#define AC_FASTAGCCONV_VAL 1 +#define AC_MIDAGCCONV_VAL 2 +#define AC_SLOWAGCCONV_VAL 3 + +#define AC_ALGOAGCTIMER_VAL 100000 +#define AC_ALGOGAINTIMER_VAL 10000 +#define AC_ALGOSITIMER_VAL 30000 +#define AC_ALGOLOCKTIMER_VAL 200000 +#define AC_ALGOLOCKCARRIER_VAL 265533 // 2*SWDYN/SWSTEP*SWLENGTH + +#define AC_COEFTRESHOLD_VAL 490000 //562500 + +#define AC_ALGOGAINMAX_VAL 5 +#define AC_ALGOGAINMIN_VAL 0 +#define AC_ALGOGAINSCANMIN_VAL 0 +#define AC_ALGOGAINSCANMID_VAL 2 +#define AC_ALGOGAINSCANMAX_VAL 4 + +#define AC_DVB_ROLLOFF_VAL 115 +#define AC_SCANSTEP_VAL 47 +#define AC_FREQSTEP_VAL 62 + + +/*******************/ +/* DEFINE MASKS */ +/*******************/ +#define AC_EQCONF1_POSI_MSK 0x70 +#define AC_EQCONF1_ENEQUAL_MSK 0x02 +#define AC_ADC_SW_MSK 0x30 +#define AC_GAIN_SFIL_MSK 0x10 +#define AC_CLKCONF_NDEC_MSK 0xC0 +#define AC_CARCONF_MSK 0x3F +#define AC_CONF_QAM_MSK 0x1C +#define AC_RSCONF_PVBER_MSK 0xC0 +#define AC_CPTUNCOR_CPTU_MSK 0x7F +#define AC_GAIN_GNYQ_MSK 0xE0 +#define AC_AGCCONF1_KAGC_MSK 0x03 +#define AC_GAIN_SSAT_MSK 0x03 +#define AC_SYNC_BER_MSK 0x30 +#define AC_DEMODSTAT_FEL_MSK 0x08 +#define AC_DEMODSTAT_UNCOR_MSK 0x80 +//add 10-13 +#define TDA10023_CARCONF_INVIQ_BIT 0x20 +#define TDA10023_CARCONF_AUTOINVIQ_BIT 0x40 + +#define TDA10023_GPR_CLBS_BIT 0x01 +#define TDA10023_GPR_CLBS2_BIT 0x02 +#define TDA10023_GPR_FSAMPLING_BIT 0x20 +#define TDA10023_GPR_FIRSTIF_BIT 0x40 +#define TDA10023_GPR_STDBY_BIT 0x80 + +#define TDA10023_PLL2_PDIV_MSK 0x3F +#define TDA10023_PLL2_NDIV_MSK 0xC0 +//--------------- +// DEFINE BITS +//--------------- +#define TDA10023_GPR_CLBS_BIT 0x01 +#define TDA10023_GPR_CLBS2_BIT 0x02 +#define TDA10023_GPR_FSAMPLING_BIT 0x20 +#define TDA10023_GPR_FIRSTIF_BIT 0x40 +#define TDA10023_GPR_STDBY_BIT 0x80 + +#define TDA10023_CLKCONF_DYN_BIT 0x08 + +#define TDA10023_CARCONF_INVIQ_BIT 0x20 +#define TDA10023_CARCONF_AUTOINVIQ_BIT 0x40 + +#define TDA10023_EQCONF1_ENEQUAL_BIT 0x02 +#define TDA10023_EQCONF1_ENADAPT_BIT 0x04 + +#define TDA10023_TEST_BYPIIC_BIT 0x80 + +#define TDA10023_FECDVBCFG1_CLB_CPT_TSP_BIT 0x20 + +#define TDA10023_STATUS_CARLOCK_BIT 0x02 +#define TDA10023_STATUS_FSYNC_BIT 0x04 +#define TDA10023_STATUS_FEL_BIT 0x08 +#define TDA10023_STATUS_NODVB_BIT 0x40 + +#define TDA10023_INTP1_POCLKP_BIT 0x01 + +#define TDA10023_ADC_GAINADC_BIT 0x20 +#define TDA10023_ADC_TWOS_BIT 0x08 + +#define TDA10023_EQCONF2_SGNALGO_BIT 0x20 +#define TDA10023_EQCONF2_STEPALGO_BIT 0x10 +#define TDA10023_EQCONF2_CTADAPT_BIT 0x08 + +#define TDA10023_CONTROL_OLDBYTECLK_BIT 0x80 +#define TDA10023_CONTROL_SACLK_ON_BIT 0x04 + +#define TDA10023_RESET_DVBMCNS_BIT 0x80 + +#define TDA10023_INTP2_MSBFIRSTP_BIT 0x04 + +#define TDA10023_PLL3_PDPLL_BIT 0x01 +#define TDA10023_PLL3_BYPPLL_BIT 0x02 +#define TDA10023_PLL3_LOCK_BIT 0x04 +#define TDA10023_PLL3_PSACLK_BIT 0x08 + +#define TDA10023_INTS1_POCLKS_BIT 0x01 + +#define TDA10023_INTPS_TRIS_BIT 0x01 +#define TDA10023_INTPS_TRIP_BIT 0x02 +#define TDA10023_INTPS_MSBFIRSTS_BIT 0x40 + +#define TDA10023_AGCCONF2_PPWMIF_BIT 0x02 +#define TDA10023_AGCCONF2_PPWMTUN_BIT 0x08 +#define TDA10023_AGCCONF2_ENAGCIF_BIT 0x10 +#define TDA10023_AGCCONF2_POSAGC_BIT 0x20 +#define TDA10023_AGCCONF2_TRIAGC_BIT 0x80 + +#define TDA10023_DELTAF_MSB_ALGOD_BIT 0x80 + +#define TDA10023_CTRL1_QAMMODE_BIT 0x02 + +#define TDA10023_STATUS_MCNS_MPEGLCK_BIT 0x04 +#define TDA10023_STATUS_MCNS_FRAMELCK_BIT 0x02 + +#define TDA10023_RSCFG_CLB_CPT_RSB_BIT 0x01 + +/******************/ +/* DEFINE BITS */ +/******************/ +#define AC_CONF_CLB_BIT 0x01 +#define AC_AGCCONF1_POSAGC_BIT 0x20 +#define AC_AGCCONF2_ENAGC2_BIT 0x08 +#define AC_ADC_PCLK_BIT 0x01 +#define AC_TEST_BYPIIC_BIT 0x80 +#define AC_EQCONF_ENEQUAL_BIT 0x02 +#define AC_CONF_INVIQ_BIT 0x20 +#define AC_RSCONF_CLBUNC_BIT 0x20 +#define AC_CLKCONF_DYN_BIT 0x08 +#define AC_SYNC_NODVB_BIT 0x40 +#define AC_CLKCONF_GAIN3_BIT 0x10 +#define AC_AGCCONF1_PPWM1_BIT 0x04 +#define AC_AGCCONF2_PPWM2_BIT 0x02 +#define AC_PLL_BYPPLL_BIT 0x10 +#define AC_POLA1_POCLK1_BIT 0x01 +#define AC_POLA2_POCLK2_BIT 0x01 +#define AC_POLA2_MSBFIRST2_BIT 0x40 +#define AC_EQCONF1_DFE_BIT 0x01 +#define AC_EQCONF1_ENEQUAL_BIT 0x02 +#define AC_EQCONF2_SGNALGO_BIT 0x20 +#define AC_EQCONF2_CTADAPT_BIT 0x08 +#define AC_DELTAF2_ALGOD_BIT 0x04 +#define AC_INTP_INTSEL_BIT 0x01 +#define AC_INTP_MSBFIRST_BIT 0x02 +#define AC_INTP_PARMOD_BIT 0x08 +#define AC_EQCONF1_ENADAPT_BIT 0x04 +#define AC_SYNC_CARLOCK_BIT 0x02 +#define AC_SYNC_FSYNC_BIT 0x04 +#define AC_SYNC_FEL_BIT 0x08 + +/*************************/ +/* DEFINE RETURN VALUES */ +/*************************/ +#define AC_SUCCESS_RET 0 +#define AC_FAILED_RET 1 +#define AC_NOT_FINISHED_RET 2 +#define AC_NO_ERROR_RET 0 + +#endif //__CU1216_REGS_H diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/frontends/dvb-pll.c kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/dvb-pll.c --- kernel-2.6.24.4-orig/drivers/media/dvb/frontends/dvb-pll.c 2008-04-05 04:21:04.000000000 +0700 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/dvb-pll.c 2008-04-03 05:09:52.000000000 +0700 @@ -229,7 +229,7 @@ }; /* Panasonic env57h1xd5 (some Philips PLL ?) */ -static struct dvb_pll_desc dvb_pll_env57h1xd5 = { +struct dvb_pll_desc dvb_pll_env57h1xd5 = { .name = "Panasonic ENV57H1XD5", .min = 44250000, .max = 858000000, diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/frontends/dvb-pll.h kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/dvb-pll.h --- kernel-2.6.24.4-orig/drivers/media/dvb/frontends/dvb-pll.h 2008-04-05 04:21:04.000000000 +0700 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/dvb-pll.h 2008-04-03 05:09:52.000000000 +0700 @@ -41,6 +41,9 @@ * @param pll_desc_id dvb_pll_desc to use. * @return Frontend pointer on success, NULL on failure */ + +extern struct dvb_pll_desc dvb_pll_env57h1xd5; + #if defined(CONFIG_DVB_PLL) || (defined(CONFIG_DVB_PLL_MODULE) && defined(MODULE)) extern struct dvb_frontend *dvb_pll_attach(struct dvb_frontend *fe, int pll_addr, diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/frontends/Kconfig kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/Kconfig --- kernel-2.6.24.4-orig/drivers/media/dvb/frontends/Kconfig 2008-04-05 04:21:04.000000000 +0700 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/Kconfig 2008-04-03 05:09:52.000000000 +0700 @@ -12,9 +12,36 @@ If unsure say N. +comment "DVB-S2 frontends" + depends on DVB_CORE + +config DVB_STB0899 + tristate "STB0899 based" + depends on DVB_CORE && I2C + default m if DVB_FE_CUSTOMISE + help + A DVB-S/S2/DSS Multistandard demodulator. Say Y when you want + to support this demodulator based frontends + comment "DVB-S (satellite) frontends" depends on DVB_CORE +config DVB_MB86A16 + tristate "Fujitsu MB86A16 based" + depends on DVB_CORE && I2C + default m + help + A DVB-S/DSS tuner module. Say Y when you want to support this frontend. + +config DVB_CU1216 + tristate "Philips CU1216 tuner based" + depends on DVB_CORE && I2C + default m + help + A DVB-C tuner module. Say Y when you want to support this frontend. + + + config DVB_STV0299 tristate "ST STV0299 based" depends on DVB_CORE && I2C diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/frontends/lg_h06xf.h kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/lg_h06xf.h --- kernel-2.6.24.4-orig/drivers/media/dvb/frontends/lg_h06xf.h 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/lg_h06xf.h 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,70 @@ +/* + * lg_h06xf.h - ATSC Tuner support for LG TDVS-H06xF + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _LG_H06XF_H_ +#define _LG_H06XF_H_ +#include "dvb-pll.h" + +static int lg_h06xf_pll_set(struct dvb_frontend* fe, struct i2c_adapter* i2c_adap, + struct dvb_frontend_parameters* params) +{ + u8 buf[4]; + struct i2c_msg msg = { .addr = 0x61, .flags = 0, + .buf = buf, .len = sizeof(buf) }; + int err; + + dvb_pll_configure(&dvb_pll_lg_tdvs_h06xf, buf, params->frequency, 0); + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if ((err = i2c_transfer(i2c_adap, &msg, 1)) != 1) { + printk(KERN_WARNING "lg_h06xf: %s error " + "(addr %02x <- %02x, err = %i)\n", + __FUNCTION__, buf[0], buf[1], err); + if (err < 0) + return err; + else + return -EREMOTEIO; + } + + /* Set the Auxiliary Byte. */ +#if 0 + buf[2] &= ~0x20; + buf[2] |= 0x18; + buf[3] = 0x50; +#else + buf[0] = buf[2]; + buf[0] &= ~0x20; + buf[0] |= 0x18; + buf[1] = 0x50; + msg.len = 2; +#endif + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if ((err = i2c_transfer(i2c_adap, &msg, 1)) != 1) { + printk(KERN_WARNING "lg_h06xf: %s error " + "(addr %02x <- %02x, err = %i)\n", + __FUNCTION__, buf[0], buf[1], err); + if (err < 0) + return err; + else + return -EREMOTEIO; + } + + return 0; +} +#endif diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/frontends/Makefile kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/Makefile --- kernel-2.6.24.4-orig/drivers/media/dvb/frontends/Makefile 2008-04-05 04:21:04.000000000 +0700 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/Makefile 2008-04-03 05:09:52.000000000 +0700 @@ -4,6 +4,9 @@ EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core/ +stb0899-objs := stb0899_core.o stb0899_drv.o stb0899_dvbs2util.o stb0899_chip.o stb0899_init.o stb0899_util.o stb0899_tuner.o + +obj-$(CONFIG_DVB_STB0899) += stb0899.o obj-$(CONFIG_DVB_PLL) += dvb-pll.o obj-$(CONFIG_DVB_STV0299) += stv0299.o obj-$(CONFIG_DVB_SP8870) += sp8870.o @@ -46,3 +49,5 @@ obj-$(CONFIG_DVB_TUA6100) += tua6100.o obj-$(CONFIG_DVB_TUNER_MT2131) += mt2131.o obj-$(CONFIG_DVB_S5H1409) += s5h1409.o +obj-$(CONFIG_DVB_MB86A16) += mb86a16.o +obj-$(CONFIG_DVB_CU1216) += cu1216.o \ В конце файла нет новой строки diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/frontends/mb86a16.c kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/mb86a16.c --- kernel-2.6.24.4-orig/drivers/media/dvb/frontends/mb86a16.c 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/mb86a16.c 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,1786 @@ +/* + Mantis PCI bridge driver + + Copyright (C) 2005, 2006 Manu Abraham (abraham.manu@gmail.com) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#include +#include +#include +#include + +#include "dvb_frontend.h" +#include "mb86a16.h" + +unsigned int verbose = 1; +module_param(verbose, int, 0644); + +#define ABS(x) ((x) < 0 ? (-x) : (x)) + +struct mb86a16_state { + struct i2c_adapter *i2c_adap; + const struct mb86a16_config *config; + struct dvb_frontend frontend; + u8 signal; + fe_sec_mini_cmd_t minicmd; + fe_sec_tone_mode_t tone; +}; + +unsigned char tmd[5] = { 0, 0, 0xff, 0xff, 0xff }; // Tone signal output signal + +#define MB86A16_ERROR 0 +#define MB86A16_NOTICE 1 +#define MB86A16_INFO 2 +#define MB86A16_DEBUG 3 + +#define dprintk(x, y, z, format, arg...) do { \ + if (z) { \ + if ((x > MB86A16_ERROR) && (x > y)) \ + printk(KERN_ERR "%s: " format "\n", __func__, ##arg); \ + else if ((x > MB86A16_NOTICE) && (x > y)) \ + printk(KERN_NOTICE "%s: " format "\n", __func__, ##arg); \ + else if ((x > MB86A16_INFO) && (x > y)) \ + printk(KERN_INFO "%s: " format "\n", __func__, ##arg); \ + else if ((x > MB86A16_DEBUG) && (x > y)) \ + printk(KERN_DEBUG "%s: " format "\n", __func__, ##arg); \ + } else { \ + if (x > y) \ + printk(format, ##arg); \ + } \ +} while (0) + +#define TRACE_IN +#define TRACE_OUT + +static int mb86a16_write(struct mb86a16_state *state, u8 reg, u8 val) +{ + int ret; + u8 buf[] = { reg, val }; + + struct i2c_msg msg = { + .addr = state->config->demod_address, + .flags = 0, + .buf = buf, + .len = 2 + }; + + dprintk(verbose, MB86A16_DEBUG, 1, + "writing to [0x%02x],Reg[0x%02x],Data[0x%02x]", + state->config->demod_address, buf[0], buf[1]); + + ret = i2c_transfer(state->i2c_adap, &msg, 1); + if (ret != 1) { + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer Error"); + return -EREMOTEIO; + } else { + //dprintk(verbose, MB86A16_DEBUG, 1, "I2C transfer successful"); + return ret; + } + + return -EIO; +} + +static int mb86a16_read(struct mb86a16_state *state, u8 reg, u8 *val) +{ + int ret; + u8 b0[] = { reg }; + u8 b1[] = { 0 }; + + struct i2c_msg msg[] = { + { + .addr = state->config->demod_address, + .flags = 0, + .buf = b0, + .len = 1 + },{ + .addr = state->config->demod_address, + .flags = I2C_M_RD, + .buf = b1, + .len = 1 + } + }; + ret = i2c_transfer(state->i2c_adap, msg, 2); + if (ret != 2) { + dprintk(verbose, MB86A16_ERROR, 1, "read error(reg=0x%02x, ret=0x%i)", + reg, ret); + + return -EREMOTEIO; + } + *val = b1[0]; + + return ret; +} + +// Antenna Set, DiSEqC signal setting +static int mb86a16_send_diseqc_msg(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd *m) +{ + struct mb86a16_state* state = fe->demodulator_priv; + u8 diseqc_reg; + unsigned char i=0; + + // write 1 to prepare outputs diseqc signal + if (mb86a16_write(state, 0x16, 0x80) != 1) + goto err; + // DiSEQc mode off, output close + if (mb86a16_write(state, 0x1e, 0) != 1) + goto err; + // TONE signal setting #2, tone output is fix low + if (mb86a16_write(state, 0x20, 0x04) != 1) + goto err; + + msleep_interruptible(10); + + diseqc_reg = 0x18; + if(m->msg_len >5 || m->msg_len <3) + return -1; + for (i=0; imsg_len; i++) { + if (mb86a16_write(state, diseqc_reg, m->msg[i]) != 1) + goto err; + diseqc_reg++; + } + i+=0x90; + msleep(10); + + if (mb86a16_write(state, 0x16, i) != 1) + goto err; + if (mb86a16_write(state, 0x1e, 0x1) != 1) + goto err; + + return 0; + +err: + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; +} + +static int mb86a16_send_diseqc_burst (struct dvb_frontend* fe, fe_sec_mini_cmd_t burst) +{ + struct mb86a16_state* state = fe->demodulator_priv; + + msleep(100); + state->minicmd = burst; + switch (burst) { + case SEC_MINI_A: + dprintk(verbose, MB86A16_DEBUG, 1, "SEC_MINI_A"); + if (mb86a16_write(state, 0x16, 0x98) != 1) + goto err; + if (mb86a16_write(state, 0x1e, 0x01) != 1) + goto err; + break; + case SEC_MINI_B: + dprintk(verbose, MB86A16_DEBUG, 1, "SEC_MINI_B"); + if (mb86a16_write(state, 0x16, 0x90) != 1) + goto err; + if (mb86a16_write(state, 0x1e, 0x01) != 1) + goto err; + break; + } + return 0; + +err: + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; +} + +// Antenna set, TONE signal Setting +static int mb86a16_send_tone_msg(struct dvb_frontend* fe, fe_sec_tone_mode_t tone) +{ + struct mb86a16_state* state = fe->demodulator_priv; + + state->tone = tone; + msleep(100); + switch (tone) { + case SEC_TONE_ON: + dprintk(verbose, MB86A16_DEBUG, 1, "SEC_TONE_ON"); + if (mb86a16_write(state, 0x20, 0x00) != 1) + goto err; + if (mb86a16_write(state, 0x16, 0xa0) != 1) + goto err; + if (mb86a16_write(state, 0x1e, 0x01) != 1) + goto err; + break; + case SEC_TONE_OFF: + dprintk(verbose, MB86A16_DEBUG, 1, "SEC_TONE_OFF"); + if (mb86a16_write(state, 0x20, 0x04) != 1) + goto err; + if (mb86a16_write(state, 0x16, 0x80) != 1) + goto err; + if (mb86a16_write(state, 0x1e, 0x00) != 1) + goto err; + break; + default: + return -EINVAL; + } + return 0; + +err: + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; +} + + +static int CNTM_set(struct mb86a16_state *state, + unsigned char timint1, + unsigned char timint2, + unsigned char cnext) +{ + unsigned char val; + + val = (timint1 << 4) | (timint2 << 2) | cnext; + if (mb86a16_write(state, 0x36, val) != 1) + goto err; + + return 0; + +err: + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; +} + +static int smrt_set(struct mb86a16_state *state, + int sr, + int DECI, + int CSEL, + int RSEL, + int clkmst) +{ + int tmp ; + int m ; + unsigned char STOFS0, STOFS1; + int ack = 1 ; + + m = 1 << DECI; + tmp = (8192 * clkmst - 2 * m * sr * 8192 + clkmst / 2) / clkmst; + + STOFS0 = tmp & 0x0ff; + STOFS1 = (tmp & 0xf00) >> 8; + + if (mb86a16_write(state, 0x03, (DECI << 2) | (CSEL << 1) | RSEL) != 1) + ack = 0; + if (mb86a16_write(state, 0x04, STOFS0) != 1) + ack = 0; + if (mb86a16_write(state, 0x05, STOFS1) != 1) + ack = 0; + + if (ack == 0) { + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -1; + } + + return 0; +} + +static int srst(struct mb86a16_state *state) +{ + if (mb86a16_write(state, 0x0c, 0x04) != 1) + goto err; + + return 0; +err: + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; + +} + +static int afcex_data_set(struct mb86a16_state *state, + unsigned char AFCEX_L, + unsigned char AFCEX_H) +{ + if (mb86a16_write(state, 0x2b, AFCEX_L) != 1) + goto err; + if (mb86a16_write(state, 0x2c, AFCEX_H) != 1) + goto err; + + return 0; +err: + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + + return -1; +} + +static int afcofs_data_set(struct mb86a16_state *state, + unsigned char AFCEX_L, + unsigned char AFCEX_H) +{ + if (mb86a16_write(state, 0x58, AFCEX_L) != 1) + goto err; + + if (mb86a16_write(state, 0x59, AFCEX_H) != 1) + goto err; + + return 0; +err: + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; +} + +static int stlp_set(struct mb86a16_state *state, + unsigned char STRAS, + unsigned char STRBS) +{ + if (mb86a16_write(state, 0x0a, (STRBS << 3) | (STRAS)) != 1) + goto err; + + return 0; +err: + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; +} + +static int Vi_set(struct mb86a16_state *state, unsigned char ETH, unsigned char VIA) +{ + // ETH = 4 + if (mb86a16_write(state, 0x3b, 0x04) != 1) + goto err; + // VIA = 5 + if (mb86a16_write(state, 0x3c, 0xf5) != 1) + goto err; + + return 0; +err: + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; +} + +static int initial_set(struct mb86a16_state *state) +{ + //int i; + //printk("%s: Initializing ..\n", __func__); + //printk(KERN_ERR "Initializing testing \n"); + //for(i=0; i<452; i++) + //{ + // mb86a16_write(state, 0x08, 0x16); + //} + //printk(KERN_ERR "Initializing testing \n"); + // Timing recovery + if (stlp_set(state, 5, 7)) + goto err; + if (afcex_data_set(state, 0, 0)) + goto err; + if (afcofs_data_set(state, 0, 0)) + goto err; + + // CRBS = 2, CRAS = 6 + if (mb86a16_write(state, 0x08, 0x16) != 1) + goto err; + + // CRWS = 1 // was 2 (0x22) + if (mb86a16_write(state, 0x2f, 0x21) != 1) + goto err; + + // VMAG = 7 + if (mb86a16_write(state, 0x39, 0x38) != 1) + goto err; + + // Front AGC Setting 1 + if (mb86a16_write(state, 0x3d, 0x00) != 1) + goto err; + // Front AGC Setting 2(4 to 3) + if (mb86a16_write(state, 0x3e, 0x1c) != 1) + goto err; + // Front AGC Setting 3(3 to 2) + if (mb86a16_write(state, 0x3f, 0x20) != 1) + goto err; + // Front AGC Setting 4(3 to 4) + if (mb86a16_write(state, 0x40, 0x1e) != 1) + goto err; + //Front AGC Setting 5(2 to 3) + if (mb86a16_write(state, 0x41, 0x23) != 1) + goto err; + if (mb86a16_write(state, 0x54, 0xff) != 1) + goto err; + // TS Output + if (mb86a16_write(state, 0x00, 0x00) != 1) + goto err; + + return 0; + +err: + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; +} + +static int S01T_set(struct mb86a16_state *state, + unsigned char s1t, + unsigned s0t) +{ + if (mb86a16_write(state, 0x33, (s1t << 3) | s0t) != 1) + goto err; + + return 0; +err: + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; +} + +static int EN_set(struct mb86a16_state *state, + int cren, + int afcen) +{ + unsigned char val; + + val = 0x7a | (cren << 7) | (afcen << 2); + if (mb86a16_write(state, 0x49, val) != 1) + goto err; + + return 0; +err: + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; +} + +static int AFCEXEN_set(struct mb86a16_state *state, + int afcexen, + int smrt) +{ + unsigned char AFCA ; + + if (smrt > 18875) + AFCA = 4; + else if (smrt > 9375) + AFCA = 3; + else if (smrt > 2250) + AFCA = 2; + else + AFCA = 1; + + if (mb86a16_write(state, 0x2a, 0x02 | (afcexen << 5) | (AFCA << 2)) != 1) + goto err; + + return 0; + +err: + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; +} + +static int DAGC_data_set(struct mb86a16_state *state, + unsigned char DAGCA, + unsigned char DAGCW) +{ + if (mb86a16_write(state, 0x2d, (DAGCA << 3) | DAGCW) != 1) + goto err; + + return 0; + +err: + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; +} + +static void smrt_info_get(struct mb86a16_state *state, + int sr, + unsigned char *DECI, + unsigned char *CSEL, + unsigned char *RSEL, + int *clkmst) +{ + if (sr >= 37501) { + *DECI = 0; *CSEL = 0; *RSEL = 0; + } else if (sr >= 30001) { + *DECI = 0; *CSEL = 0; *RSEL = 1; + } else if (sr >= 26251) { + *DECI = 0; *CSEL = 1; *RSEL = 0; + } else if (sr >= 22501) { + *DECI = 0; *CSEL = 1; *RSEL = 1; + } else if (sr >= 18751) { + *DECI = 1; *CSEL = 0; *RSEL = 0; + } else if (sr >= 15001) { + *DECI = 1; *CSEL = 0; *RSEL = 1; + } else if (sr >= 13126) { + *DECI = 1; *CSEL = 1; *RSEL = 0; + } else if (sr >= 11251) { + *DECI = 1; *CSEL = 1; *RSEL = 1; + } else if (sr >= 9376) { + *DECI = 2; *CSEL = 0; *RSEL = 0; + } else if (sr >= 7501) { + *DECI = 2; *CSEL = 0; *RSEL = 1; + } else if (sr >= 6563) { + *DECI = 2; *CSEL = 1; *RSEL = 0; + } else if (sr >= 5626) { + *DECI = 2; *CSEL = 1; *RSEL = 1; + } else if (sr >= 4688) { + *DECI = 3; *CSEL = 0; *RSEL = 0; + } else if (sr >= 3751) { + *DECI = 3; *CSEL = 0; *RSEL = 1; + } else if (sr >= 3282) { + *DECI = 3; *CSEL = 1; *RSEL = 0; + } else if (sr >= 2814) { + *DECI = 3; *CSEL = 1; *RSEL = 1; + } else if (sr >= 2344) { + *DECI = 4; *CSEL = 0; *RSEL = 0; + } else if (sr >= 1876) { + *DECI = 4; *CSEL = 0; *RSEL = 1; + } else if (sr >= 1641) { + *DECI = 4; *CSEL = 1; *RSEL = 0; + } else if (sr >= 1407) { + *DECI = 4; *CSEL = 1; *RSEL = 1; + } else if (sr >= 1172) { + *DECI = 5; *CSEL = 0; *RSEL = 0; + } else if (sr >= 939) { + *DECI = 5; *CSEL = 0; *RSEL = 1; + } else if (sr >= 821) { + *DECI = 5; *CSEL = 1; *RSEL = 0; + } else { + *DECI = 5; *CSEL = 1; *RSEL = 1; + } + + if (*CSEL == 0) + *clkmst = 92000; + else + *clkmst = 61333; + +} + +static int signal_det(struct mb86a16_state *state, + int smrt, unsigned char *DECI, + unsigned char *CSEL, + unsigned char *RSEL, + int *clkmst, + unsigned char *SIG) +{ + + int ret ; + int smrtd ; + int wait_sym ; + int wait_t ; + unsigned char S[3] ; + int i ; + + if (*SIG > 45) { + if (CNTM_set(state, 2, 1, 2) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error"); + return -1; + } + wait_sym = 40000; + } else { + if (CNTM_set(state, 3, 1, 2) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error"); + return -1; + } + wait_sym = 80000; + } + for (i = 0; i < 3; i++) { + if (i == 0 ) + smrtd = smrt * 98 / 100; + else if (i == 1) + smrtd = smrt; + else + smrtd = smrt * 102 / 100; + smrt_info_get(state, smrtd, DECI, CSEL, RSEL, clkmst); + smrt_set(state, smrtd, *DECI, *CSEL, *RSEL, *clkmst); + srst(state); + wait_t = (wait_sym + 99 * smrtd / 100) / smrtd; + if (wait_t == 0) + wait_t = 1; + msleep_interruptible(10); + if (mb86a16_read(state, 0x37, &(S[i])) != 2) { + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; + } + } + if ((S[1] > S[0] * 112 / 100) && + (S[1] > S[2] * 112 / 100)) { + + ret = 1; + } else { + ret = 0; + } + *SIG = S[1]; + + if (CNTM_set(state, 0, 1, 2) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error"); + return -1; + } + + return ret; +} + +static int rf_val_set(struct mb86a16_state *state, + int f, + int smrt, + unsigned char R) +{ + unsigned char C, F, B; + int M; + unsigned char rf_val[5]; + int ack = -1; + + if (smrt > 37750 ) + C = 1; + else if (smrt > 18875) + C = 2; + else if (smrt > 5500 ) + C = 3; + else + C = 4; + + if (smrt > 30500) + F = 3; + else if (smrt > 9375) + F = 1; + else if (smrt > 4625) + F = 0; + else + F = 2; + + if (f < 1060) + B = 0; + else if (f < 1175) + B = 1; + else if (f < 1305) + B = 2; + else if (f < 1435) + B = 3; + else if (f < 1570) + B = 4; + else if (f < 1715) + B = 5; + else if (f < 1845) + B = 6; + else if (f < 1980) + B = 7; + else if (f < 2080) + B = 8; + else + B = 9; + + M = f * (1 << R) / 2; + + rf_val[0] = 0x01 | (C << 3) | (F << 1); + rf_val[1] = (R << 5) | ((M & 0x1f000) >> 12); + rf_val[2] = (M & 0x00ff0) >> 4; + rf_val[3] = ((M & 0x0000f) << 4) | B; + + // Frequency Setting #1 #2 #3 #4 and frequency Setting Switch + if (mb86a16_write(state, 0x21, rf_val[0]) != 1) + ack = 0; + if (mb86a16_write(state, 0x22, rf_val[1]) != 1) + ack = 0; + if (mb86a16_write(state, 0x23, rf_val[2]) != 1) + ack = 0; + if (mb86a16_write(state, 0x24, rf_val[3]) != 1) + ack = 0; + if (mb86a16_write(state, 0x25, 0x01) != 1) + ack = 0; + if (ack == 0) { + dprintk(verbose, MB86A16_ERROR, 1, "rf_val_set - I2C transfer error"); + return -EREMOTEIO; + } + + return 0; +} + +static int afcerr_chk(struct mb86a16_state *state, + int clkmst) +{ + unsigned char AFCM_L, AFCM_H ; + int AFCM ; + int afcm, afcerr ; + + if (mb86a16_read(state, 0x0e, &AFCM_L) != 2) + goto err; + if (mb86a16_read(state, 0x0f, &AFCM_H) != 2) + goto err; + + AFCM = (AFCM_H << 8) + AFCM_L; + + if (AFCM > 2048) + afcm = AFCM - 4096; + else + afcm = AFCM; + afcerr = afcm * clkmst / 8192; + + return afcerr; + +err: + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; +} + +static int dagcm_val_get(struct mb86a16_state *state) +{ + int DAGCM; + unsigned char DAGCM_H, DAGCM_L; + + if (mb86a16_read(state, 0x45, &DAGCM_L) != 2) + goto err; + if (mb86a16_read(state, 0x46, &DAGCM_H) != 2) + goto err; + + DAGCM = (DAGCM_H << 8) + DAGCM_L; + + return DAGCM; + +err: + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; +} + +static int mb86a16_read_status(struct dvb_frontend *fe, fe_status_t *status) +{ + struct mb86a16_state *state = fe->demodulator_priv; + + *status = 0; + if (mb86a16_read(state, 0x0d, &state->signal) != 2) + goto err; + + if (state->signal & 0x02) + *status |= FE_HAS_VITERBI; + if (state->signal & 0x01) + *status |= FE_HAS_SYNC; + if (state->signal & 0x03) + { + *status |= FE_HAS_SIGNAL; + *status |= FE_HAS_LOCK; + *status |= FE_HAS_CARRIER; + } + return 0; +err: + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; +} + +static int sync_chk(struct mb86a16_state *state, + unsigned char *VIRM) +{ + int sync ; + + if (mb86a16_read(state, 0x0d, &state->signal) != 2) + goto err; + + dprintk(verbose, MB86A16_INFO, 1, "Status = %02x,", state->signal); + sync = state->signal & 0x01; + *VIRM = (state->signal & 0x1c) >> 2; + + return sync; +err: + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; + +} + +static int freqerr_chk(struct mb86a16_state *state, + int fTP, + int smrt, + int unit) +{ + unsigned char CRM, AFCML, AFCMH; + unsigned char temp1, temp2, temp3; + unsigned char DECI, CSEL, RSEL; + int clkmst; + int crm, afcm, AFCM; + int crrerr, afcerr; // [kHz] + int frqerr; // [MHz] + int afcen, afcexen = 0; + int R, M, fOSC, fOSC_OFS; + + if (mb86a16_read(state, 0x43, &CRM) != 2) + goto err; + + if (CRM > 127) + crm = CRM - 256; + else + crm = CRM; + + crrerr = smrt * crm / 256; + if (mb86a16_read(state, 0x49, &temp1) != 2) + goto err; + + afcen = (temp1 & 0x04) >> 2; + if (afcen == 0) { + if (mb86a16_read(state, 0x2a, &temp1) != 2) + goto err; + afcexen = (temp1 & 0x20) >> 5; + } + + if (afcen == 1) { + if (mb86a16_read(state, 0x0e, &AFCML) != 2) + goto err; + if (mb86a16_read(state, 0x0f, &AFCMH) != 2) + goto err; + } else if (afcexen == 1) { + if (mb86a16_read(state, 0x2b, &AFCML) != 2) + goto err; + if (mb86a16_read(state, 0x2c, &AFCMH) != 2) + goto err; + } + if ((afcen == 1) || (afcexen == 1)) { + smrt_info_get(state, smrt, &DECI, &CSEL, &RSEL, &clkmst); + AFCM = ((AFCMH & 0x01) << 8) + AFCML; + if (AFCM > 255) + afcm = AFCM - 512; + else + afcm = AFCM; + + afcerr = afcm * clkmst / 8192; + } else + afcerr = 0; + + if (mb86a16_read(state, 0x22, &temp1) != 2) + goto err; + if (mb86a16_read(state, 0x23, &temp2) != 2) + goto err; + if (mb86a16_read(state, 0x24, &temp3) != 2) + goto err; + + R = (temp1 & 0xe0) >> 5; + M = ((temp1 & 0x1f) << 12) + (temp2 << 4) + (temp3 >> 4); + if (R == 0) + fOSC = 2 * M; + else + fOSC = M; + + fOSC_OFS = fOSC - fTP; + + if (unit == 0) { //[MHz] + if (crrerr + afcerr + fOSC_OFS * 1000 >= 0) + frqerr = (crrerr + afcerr + fOSC_OFS * 1000 + 500) / 1000; + else + frqerr = (crrerr + afcerr + fOSC_OFS * 1000 - 500) / 1000; + } else { //[kHz] + frqerr = crrerr + afcerr + fOSC_OFS * 1000; + } + + return frqerr; +err: + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; +} + +static unsigned char vco_dev_get(struct mb86a16_state *state, int smrt) +{ + unsigned char R; + + if (smrt > 9375) + R = 0; + else + R = 1; + + return R; +} + +static void swp_info_get(struct mb86a16_state *state, + int fOSC_start, + int smrt, int clkmst, + int v, int R, + int swp_ofs, + int *fOSC, + int *afcex_freq, + unsigned char *AFCEX_L, + unsigned char *AFCEX_H) +{ + int AFCEX ; + int crnt_swp_freq ; + + crnt_swp_freq = fOSC_start * 1000 + v * swp_ofs; + + if (R == 0 ) + *fOSC = (crnt_swp_freq + 1000) / 2000 * 2; + else + *fOSC = (crnt_swp_freq + 500) / 1000; + + if (*fOSC >= crnt_swp_freq) + *afcex_freq = *fOSC *1000 - crnt_swp_freq; + else + *afcex_freq = crnt_swp_freq - *fOSC * 1000; + + AFCEX = *afcex_freq * 8192 / clkmst; + *AFCEX_L = AFCEX & 0x00ff; + *AFCEX_H = (AFCEX & 0x0f00) >> 8; +} + + +static int swp_freq_calcuation(struct mb86a16_state *state, int i, int v, int *V, int vmax, int vmin, + int SIGMIN, int fOSC, int afcex_freq, int swp_ofs, unsigned char *SIG1) +{ + int swp_freq ; + + if ((i % 2 == 1) && (v <= vmax)) { + // positive v (case 1) + if ((v - 1 == vmin) && + (*(V + 30 + v) >= 0) && + (*(V + 30 + v - 1) >= 0) && + (*(V + 30 + v - 1) > *(V + 30 + v)) && + (*(V + 30 + v - 1) > SIGMIN)) { + + swp_freq = fOSC * 1000 + afcex_freq - swp_ofs; + *SIG1 = *(V + 30 + v - 1); + } else if ((v == vmax) && + (*(V + 30 + v) >= 0) && + (*(V + 30 + v - 1) >= 0) && + (*(V + 30 + v) > *(V + 30 + v - 1)) && + (*(V + 30 + v) > SIGMIN)) { + // (case 2) + swp_freq = fOSC * 1000 + afcex_freq; + *SIG1 = *(V + 30 + v); + } else if ((*(V + 30 + v) > 0) && + (*(V + 30 + v - 1) > 0) && + (*(V + 30 + v - 2) > 0) && + (*(V + 30 + v - 3) > 0) && + (*(V + 30 + v - 1) > *(V + 30 + v)) && + (*(V + 30 + v - 2) > *(V + 30 + v - 3)) && + ((*(V + 30 + v - 1) > SIGMIN) || + (*(V + 30 + v - 2) > SIGMIN))) { + // (case 3) + if (*(V + 30 + v - 1) >= *(V + 30 + v - 2)) { + swp_freq = fOSC * 1000 + afcex_freq - swp_ofs; + *SIG1 = *(V + 30 + v - 1); + } else { + swp_freq = fOSC * 1000 + afcex_freq - swp_ofs * 2; + *SIG1 = *(V + 30 + v - 2); + } + } else if ((v == vmax) && + (*(V + 30 + v) >= 0) && + (*(V + 30 + v - 1) >= 0) && + (*(V + 30 + v - 2) >= 0) && + (*(V + 30 + v) > *(V + 30 + v - 2)) && + (*(V + 30 + v - 1) > *(V + 30 + v - 2)) && + ((*(V + 30 + v) > SIGMIN) || + (*(V + 30 + v - 1) > SIGMIN))) { + // (case 4) + if (*(V + 30 + v) >= *(V + 30 + v - 1)) { + swp_freq = fOSC * 1000 + afcex_freq; + *SIG1 = *(V + 30 + v); + } else { + swp_freq = fOSC * 1000 + afcex_freq - swp_ofs; + *SIG1 = *(V + 30 + v - 1); + } + } else { + swp_freq = -1 ; + } + } else if ((i % 2 == 0) && (v >= vmin)) { + // Negative v (case 1) + if ((*(V + 30 + v) > 0) && + (*(V + 30 + v + 1) > 0) && + (*(V + 30 + v + 2) > 0) && + (*(V + 30 + v + 1) > *(V + 30 + v)) && + (*(V + 30 + v + 1) > *(V + 30 + v + 2)) && + (*(V + 30 + v + 1) > SIGMIN)) { + + swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; + *SIG1 = *(V + 30 + v + 1); + } else if ((v + 1 == vmax) && + (*(V + 30 + v) >= 0) && + (*(V + 30 + v + 1) >= 0) && + (*(V + 30 + v + 1) > *(V + 30 + v)) && + (*(V + 30 + v + 1) > SIGMIN)) { + // (case 2) + swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; + *SIG1 = *(V + 30 + v); + } else if ((v == vmin) && + (*(V + 30 + v) > 0) && + (*(V + 30 + v + 1) > 0) && + (*(V + 30 + v + 2) > 0) && + (*(V + 30 + v) > *(V + 30 + v + 1)) && + (*(V + 30 + v) > *(V + 30 + v + 2)) && + (*(V + 30 + v) > SIGMIN)) { + // (case 3) + swp_freq = fOSC * 1000 + afcex_freq; + *SIG1 = *(V + 30 + v); + } else if ((*(V + 30 + v) >= 0) && + (*(V + 30 + v + 1) >= 0) && + (*(V + 30 + v + 2) >= 0) && + (*(V +30 + v + 3) >= 0) && + (*(V + 30 + v + 1) > *(V + 30 + v)) && + (*(V + 30 + v + 2) > *(V + 30 + v + 3)) && + ((*(V + 30 + v + 1) > SIGMIN) || + (*(V + 30 + v + 2) > SIGMIN))) { + // (case 4) + if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) { + swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; + *SIG1 = *(V + 30 + v + 1); + } else { + swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2; + *SIG1 = *(V + 30 + v + 2); + } + } else if ((*(V + 30 + v) >= 0) && + (*(V + 30 + v + 1) >= 0) && + (*(V + 30 + v + 2) >= 0) && + (*(V + 30 + v + 3) >= 0) && + (*(V + 30 + v) > *(V + 30 + v + 2)) && + (*(V + 30 + v + 1) > *(V + 30 + v + 2)) && + (*(V + 30 + v) > *(V + 30 + v + 3)) && + (*(V + 30 + v + 1) > *(V + 30 + v + 3)) && + ((*(V + 30 + v) > SIGMIN) || + (*(V + 30 + v + 1) > SIGMIN))) { + // (case 5) + if (*(V + 30 + v) >= *(V + 30 + v + 1)) { + swp_freq = fOSC * 1000 + afcex_freq; + *SIG1 = *(V + 30 + v); + } else { + swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; + *SIG1 = *(V + 30 + v + 1); + } + } else if ((v + 2 == vmin) && + (*(V + 30 + v) >= 0) && + (*(V + 30 + v + 1) >= 0) && + (*(V + 30 + v + 2) >= 0) && + (*(V + 30 + v + 1) > *(V + 30 + v)) && + (*(V + 30 + v + 2) > *(V + 30 + v)) && + ((*(V + 30 + v + 1) > SIGMIN) || + (*(V + 30 + v + 2) > SIGMIN))) { + // (case 6) + if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) { + swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; + *SIG1 = *(V + 30 + v + 1); + } else { + swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2; + *SIG1 = *(V + 30 + v + 2); + } + } else if ((vmax == 0) && (vmin == 0) && (*(V + 30 + v) > SIGMIN)) { + swp_freq = fOSC * 1000; + *SIG1 = *(V + 30 + v); + } else swp_freq = -1; + } else swp_freq = -1; + + return swp_freq; +} + + +static void swp_info_get2(struct mb86a16_state *state, + int smrt, + int R, + int swp_freq, + int clkmst, + int *afcex_freq, + int *fOSC, + unsigned char *AFCEX_L, + unsigned char *AFCEX_H) +{ + int AFCEX ; + + if (R == 0) + *fOSC = (swp_freq + 1000) / 2000 * 2; + else + *fOSC = (swp_freq + 500) / 1000; + + if (*fOSC >= swp_freq) + *afcex_freq = *fOSC * 1000 - swp_freq; + else + *afcex_freq = swp_freq - *fOSC * 1000; + + AFCEX = *afcex_freq * 8192 / clkmst; + *AFCEX_L = AFCEX & 0x00ff; + *AFCEX_H = (AFCEX & 0x0f00) >> 8; +} + +static void afcex_info_get(struct mb86a16_state *state, + int clkmst, + int afcex_freq, + unsigned char *AFCEX_L, + unsigned char *AFCEX_H) +{ + int AFCEX ; + + AFCEX = afcex_freq * 8192 / clkmst; + *AFCEX_L = AFCEX & 0x00ff; + *AFCEX_H = (AFCEX & 0x0f00) >> 8; +} + +static int SEQ_set(struct mb86a16_state *state, unsigned char loop) +{ + // SLOCK0 = 0 + if (mb86a16_write(state, 0x32, 0x02 | (loop << 2)) != 1) { + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; + } + + return 0; +} + +static int iq_vt_set(struct mb86a16_state *state, unsigned char IQINV) +{ + // Viterbi Rate, IQ Settings + if (mb86a16_write(state, 0x06, 0xdf | (IQINV << 5)) != 1) { + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; + } + + return 0; +} + +static int FEC_srst(struct mb86a16_state *state) +{ + if (mb86a16_write(state, 0x0c, 0x02) != 1) { + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; + } + + return 0; +} + +static int S2T_set(struct mb86a16_state *state, unsigned char S2T) +{ + if (mb86a16_write(state, 0x34, 0x70 | S2T) != 1) { + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; + } + + return 0; +} + +static int S45T_set(struct mb86a16_state *state, unsigned char S4T, unsigned char S5T) +{ + if (mb86a16_write(state, 0x35, 0x00 | (S5T << 4) | S4T) != 1) { + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; + } + + return 0; +} + + +static int mb86a16_set_fe(struct mb86a16_state *state, + u32 freq, + u32 symb) +{ + u8 agcval, cnmval; + + int fTP, smrt; + int i, j; + int fOSC = 0; + int fOSC_start = 0; + int clkmst; //internal clock freq[kHz] + int wait_t; + int fcp; + int swp_ofs; + int V[60]; + u8 SIG1MIN; + + unsigned char DECI, CSEL, RSEL; + unsigned char CREN, AFCEN, AFCEXEN; + unsigned char SIG1; + unsigned char TIMINT1, TIMINT2, TIMEXT; + unsigned char S0T, S1T; + unsigned char S2T; + unsigned char S4T, S5T; + unsigned char AFCEX_L, AFCEX_H; + unsigned char R; + unsigned char VIRM; + unsigned char ETH, VIA; + unsigned char junk; + + int loop; + int ftemp; + int v, vmax, vmin; + int vmax_his, vmin_his; + int swp_freq, prev_swp_freq[20]; + int prev_freq_num; + int signal_dupl; + int afcex_freq; + int signal; + int afcerr; + int temp_freq, delta_freq; + int dagcm[4]; + int smrt_d; + int ret = -1; + int sync; + + fTP = (int) freq / 1000; + smrt = (int) symb / 1000; + + dprintk(verbose, MB86A16_DEBUG, 1, "freq=%d Mhz, symbrt=%d Ksps", fTP, smrt); + + fcp = 3000; //capture range of carrier recovery[kHz] + swp_ofs = smrt / 4; + + for (i = 0; i < 60; i++) + V[i] = -1; + + for (i = 0; i < 20; i++) + prev_swp_freq[i] = 0; + + SIG1MIN = 25; + + + SEQ_set(state, 0); + iq_vt_set(state, 0); + + CREN = 0; + AFCEN = 0; + AFCEXEN = 1; + TIMINT1 = 0; + TIMINT2 = 1; + TIMEXT = 2; + S1T = 0; + S0T = 0; + + if (initial_set(state) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "initial set failed"); + return -1; + } + if (DAGC_data_set(state, 3, 2) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error"); + return -1; + } + if (EN_set(state, CREN, AFCEN) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "EN set error"); + return -1; // (0, 0) + } + if (AFCEXEN_set(state, AFCEXEN, smrt) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); + return -1; // (1, smrt) = (1, symbolrate) + } + if (CNTM_set(state, TIMINT1, TIMINT2, TIMEXT) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "CNTM set error"); + return -1; // (0, 1, 2) + } + if (S01T_set(state, S1T, S0T) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "S01T set error"); + return -1; // (0, 0) + } + smrt_info_get(state, smrt, &DECI, &CSEL, &RSEL, &clkmst); + if (smrt_set(state, smrt, DECI, CSEL, RSEL, clkmst) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "smrt info get error"); + return -1; + } + + R = vco_dev_get(state, smrt); + if (R == 1) + fOSC_start = fTP; + else if (R == 0) { + if (fTP % 2 == 0) { + fOSC_start = fTP; + } else { + fOSC_start = fTP + 1; + if (fOSC_start > 2150) + fOSC_start = fTP - 1; + } + } + loop = 1; + ftemp = fOSC_start * 1000; + vmax = 0 ; + while (loop == 1) { + ftemp = ftemp + swp_ofs; + vmax++; + + // Upper bound + if (ftemp > 2150000) { + loop = 0; + vmax--; + } + else if ((ftemp == 2150000) || (ftemp - fTP * 1000 >= fcp + smrt / 4)) + loop = 0; + } + + loop = 1; + ftemp = fOSC_start * 1000; + vmin = 0 ; + while (loop == 1) { + ftemp = ftemp - swp_ofs; + vmin--; + + // Lower bound + if (ftemp < 950000) { + loop = 0; + vmin++; + } + else if ((ftemp == 950000) || (fTP * 1000 - ftemp >= fcp + smrt / 4)) + loop = 0; + } + + wait_t = (8000 + smrt / 2) / smrt; + if (wait_t == 0) + wait_t = 1; + + i = 0; + j = 0; + prev_freq_num = 0; + loop = 1; + signal = 0; + vmax_his = 0; + vmin_his = 0; + v = 0; + + while (loop == 1) { + swp_info_get(state, fOSC_start, smrt, clkmst, + v, R, swp_ofs, &fOSC, + &afcex_freq, &AFCEX_L, &AFCEX_H); + + if (rf_val_set(state, fOSC, smrt,R) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); + return -1; + } + + if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); + return -1; + } + if (srst(state) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "srst error"); + return -1; + } + msleep_interruptible(wait_t); + + if (mb86a16_read(state, 0x37, &SIG1) != 2) { + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -1; + } + V[30 + v] = SIG1 ; + swp_freq = swp_freq_calcuation(state, i, v, V, vmax, vmin, + SIG1MIN, fOSC, afcex_freq, + swp_ofs, &SIG1); //changed + + signal_dupl = 0; + for (j = 0; j < prev_freq_num; j++) { + if ((ABS(prev_swp_freq[j] - swp_freq)) < (swp_ofs * 3 / 2)) { + signal_dupl = 1; + dprintk(verbose, MB86A16_INFO, 1, "Probably Duplicate Signal, j = %d", j); + } + } + if ((signal_dupl == 0) && (swp_freq > 0) && (ABS(swp_freq - fTP * 1000) < fcp + smrt / 6)) { + dprintk(verbose, MB86A16_DEBUG, 1, "------ Signal detect ------ [swp_freq=[%07d, srate=%05d]]", swp_freq, smrt); + prev_swp_freq[prev_freq_num] = swp_freq; + prev_freq_num++; + swp_info_get2(state, smrt, R, swp_freq, clkmst, + &afcex_freq, &fOSC, + &AFCEX_L, &AFCEX_H); + + if (rf_val_set(state, fOSC, smrt, R) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); + return -1; + } + if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); + return -1; + } + signal = signal_det(state, smrt, &DECI, &CSEL, &RSEL, &clkmst, &SIG1); + if (signal == 1) { + dprintk(verbose, MB86A16_DEBUG, 1, "***** Signal Found *****"); + loop = 0; + } else { + dprintk(verbose, MB86A16_ERROR, 1, "!!!!! No signal !!!!!, try again..."); + smrt_info_get(state, smrt, &DECI, &CSEL, &RSEL, &clkmst); + if (smrt_set(state, smrt, DECI, CSEL, RSEL, clkmst) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); + return -1; + } + } + } + if (v > vmax) + vmax_his = 1 ; + if (v < vmin) + vmin_his = 1 ; + i++; + + if ((i % 2 == 1) && (vmax_his == 1)) + i++; + if ((i % 2 == 0) && (vmin_his == 1)) + i++; + + if (i % 2 == 1) + v = (i + 1) / 2; + else + v = -i / 2; + + if ((vmax_his == 1) && (vmin_his == 1)) + loop = 0 ; + } + + if (signal == 1) { + S1T = 7 ; + S0T = 1 ; + CREN = 0 ; + AFCEN = 1 ; + AFCEXEN = 0 ; + + if (S01T_set(state, S1T, S0T) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "S01T set error"); + return -1; + } + smrt_info_get(state, smrt, &DECI, &CSEL, &RSEL, &clkmst); + if (smrt_set(state, smrt, DECI, CSEL, RSEL, clkmst) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); + return -1; + } + if (EN_set(state, CREN, AFCEN) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "EN set error"); + return -1; + } + if (AFCEXEN_set(state, AFCEXEN, smrt) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); + return -1; + } + afcex_info_get(state, clkmst, afcex_freq, &AFCEX_L, &AFCEX_H); + if (afcofs_data_set(state, AFCEX_L, AFCEX_H) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "AFCOFS data set error"); + return -1; + } + if (srst(state) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "srst error"); + return -1; + } + // delay 4~200 + wait_t = 200000 / clkmst + 200000 / smrt; + msleep(wait_t); + afcerr = afcerr_chk(state, clkmst); + if (afcerr == -1) + return -1; + + swp_freq = fOSC * 1000 + afcerr ; + AFCEXEN = 1 ; + if (smrt >= 1500) + smrt_d = smrt / 3; + else + smrt_d = smrt / 2; + smrt_info_get(state, smrt_d, &DECI, &CSEL, &RSEL, &clkmst); + if (smrt_set(state, smrt_d, DECI, CSEL, RSEL, clkmst) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); + return -1; + } + if (AFCEXEN_set(state, AFCEXEN, smrt_d) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); + return -1; + } + R = vco_dev_get(state, smrt_d); + if (DAGC_data_set(state, 2, 0) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error"); + return -1; + } + for (i = 0; i < 3; i++) { + temp_freq = swp_freq + (i - 1) * smrt / 8; + swp_info_get2(state, smrt_d, R, temp_freq, clkmst, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); + if (rf_val_set(state, fOSC, smrt_d, R) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); + return -1; + } + if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); + return -1; + } + wait_t = 200000 / clkmst + 40000 / smrt_d; + msleep(wait_t); + dagcm[i] = dagcm_val_get(state); + } + if ((dagcm[0] > dagcm[1]) && + (dagcm[0] > dagcm[2]) && + (dagcm[0] - dagcm[1] > 2 * (dagcm[2] - dagcm[1]))) { + + temp_freq = swp_freq - 2 * smrt / 8; + swp_info_get2(state, smrt_d, R, temp_freq, clkmst, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); + if (rf_val_set(state, fOSC, smrt_d, R) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); + return -1; + } + if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "afcex data set"); + return -1; + } + wait_t = 200000 / clkmst + 40000 / smrt_d; + msleep(wait_t); + dagcm[3] = dagcm_val_get(state); + if (dagcm[3] > dagcm[1]) + delta_freq = (dagcm[2] - dagcm[0] + dagcm[1] - dagcm[3]) * smrt / 300; + else + delta_freq = 0; + } else if ((dagcm[2] > dagcm[1]) && + (dagcm[2] > dagcm[0]) && + (dagcm[2] - dagcm[1] > 2 * (dagcm[0] - dagcm[1]))) { + + temp_freq = swp_freq + 2 * smrt / 8; + swp_info_get2(state, smrt_d, R, temp_freq, clkmst, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); + if (rf_val_set(state, fOSC, smrt_d, R) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "rf val set"); + return -1; + } + if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "afcex data set"); + return -1; + } + wait_t = 200000 / clkmst + 40000 / smrt_d; + msleep(wait_t); + dagcm[3] = dagcm_val_get(state); + if (dagcm[3] > dagcm[1]) + delta_freq = (dagcm[2] - dagcm[0] + dagcm[3] - dagcm[1]) * smrt / 300; + else + delta_freq = 0 ; + + } else { + delta_freq = 0 ; + } + swp_freq += delta_freq; + if (ABS(fTP * 1000 - swp_freq) > 3800) { + dprintk(verbose, MB86A16_ERROR, 1, "NO -- SIGNAL !"); + } else { + + S1T = 0; + S0T = 3; + CREN = 1; + AFCEN = 0; + AFCEXEN = 1; + + if (S01T_set(state, S1T, S0T) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "S01T set error"); + return -1; + } + if (DAGC_data_set(state, 0, 0) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error"); + return -1; + } + R = vco_dev_get(state, smrt); + smrt_info_get(state, smrt, &DECI, &CSEL, &RSEL, &clkmst); + if (smrt_set(state, smrt, DECI, CSEL, RSEL, clkmst) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); + return -1; + } + if (EN_set(state, CREN, AFCEN) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "EN set error"); + return -1; + } + if (AFCEXEN_set(state, AFCEXEN, smrt) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); + return -1; + } + swp_info_get2(state, smrt, R, swp_freq, clkmst, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); + if (rf_val_set(state, fOSC, smrt, R) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); + return -1; + } + if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); + return -1; + } + if (srst(state) < 0) { + dprintk(verbose, MB86A16_ERROR, 1, "srst error"); + return -1; + } + wait_t = 7 + (10000 + smrt / 2) / smrt; + if (wait_t == 0) + wait_t = 1; + msleep_interruptible(wait_t); + if (mb86a16_read(state, 0x37, &SIG1) != 2) { + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; + } + + if (SIG1 > 110) { + S2T = 4; S4T = 1; S5T = 6; ETH = 4; VIA = 6; + wait_t = 7 + (917504 + smrt / 2) / smrt; + } else if (SIG1 > 105) { + S2T = 4; S4T = 2; S5T = 8; ETH = 7; VIA = 2; + wait_t = 7 + (1048576 + smrt / 2) / smrt; + } else if (SIG1 > 85) { + S2T = 5; S4T = 2; S5T = 8; ETH = 7; VIA = 2; + wait_t = 7 + (1310720 + smrt / 2) / smrt; + } else if (SIG1 > 65) { + S2T = 6; S4T = 2; S5T = 8; ETH = 7; VIA = 2; + wait_t = 7 + (1572864 + smrt / 2) / smrt; + } else { + S2T = 7; S4T = 2; S5T = 8; ETH = 7; VIA = 2; + wait_t = 7 + (2097152 + smrt / 2) / smrt; + } + S2T_set(state, S2T); + S45T_set(state, S4T, S5T); + Vi_set(state, ETH, VIA); + srst(state); + msleep_interruptible(wait_t); + sync = sync_chk(state, &VIRM); + dprintk(verbose, MB86A16_DEBUG, 1, "-------- Viterbi=[%d] SYNC=[%d] ---------", VIRM, sync); + if (mb86a16_read(state, 0x0d, &state->signal) != 2) { + dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); + return -EREMOTEIO; + } + if (VIRM) { + if (VIRM == 4) { // 5/6 + if (SIG1 > 110) + wait_t = ( 786432 + smrt/2) / smrt; + else + wait_t = (1572864 + smrt/2) / smrt; + if (smrt < 5000) + // FIXME ! , should be a long wait ! + msleep_interruptible(wait_t); + else + msleep_interruptible(wait_t); + + if (sync_chk(state, &junk) == 0) { + iq_vt_set(state, 1); + FEC_srst(state); + } + if (SIG1 > 110) + wait_t = ( 786432 + smrt/2) / smrt; + else + wait_t = (1572864 + smrt/2) / smrt; + + msleep_interruptible(wait_t); + SEQ_set(state, 1); + } else { // 1/2, 2/3, 3/4, 7/8 + if (SIG1 > 110) + wait_t = ( 786432 + smrt/2) / smrt; + else + wait_t = (1572864 + smrt/2) / smrt; + + msleep_interruptible(wait_t); + SEQ_set(state, 1); + } + } else { + dprintk(verbose, MB86A16_ERROR, 1, "NO -- SIGNAL"); + SEQ_set(state, 1); + } + } + } else { + dprintk (verbose, MB86A16_ERROR, 1, "NO -- SIGNAL"); + } + + sync = sync_chk(state, &junk); + if (sync) { + dprintk(verbose, MB86A16_ERROR, 1, "******* SYNC *******"); + freqerr_chk(state, fTP, smrt, 1); + } + mb86a16_read(state, 0x15, &agcval); + mb86a16_read(state, 0x26, &cnmval); + dprintk(verbose, MB86A16_DEBUG, 1, "AGC = %02x CNM = %02x", agcval, cnmval); + + return ret; +} + +#define MB86A16_FE_ALGO 1 + +static int mb86a16_frontend_algo(struct dvb_frontend *fe) +{ + return MB86A16_FE_ALGO; +} + +static int mb86a16_set_frontend(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p, + unsigned int mode_flags, + int *delay, + fe_status_t *status) +{ + int ret = 0; + struct mb86a16_state *state = fe->demodulator_priv; + + TRACE_IN; + //dprintk(verbose, MB86A16_ERROR, 1, "freq = %d symb = %d", p->frequency, p->u.qpsk.symbol_rate); + if (p != NULL) + ret = mb86a16_set_fe(state, p->frequency, p->u.qpsk.symbol_rate); + + if (!(mode_flags & FE_TUNE_MODE_ONESHOT)) + mb86a16_read_status(fe, status); + + *delay = HZ/3000; + + TRACE_OUT; + dprintk(verbose, MB86A16_DEBUG, 1, "mb86a16_set_frontend end"); + return ret; +} + +static void mb86a16_release(struct dvb_frontend *fe) +{ + struct mb86a16_state *state = fe->demodulator_priv; + kfree(state); +} + +static int mb86a16_init(struct dvb_frontend *fe) +{ + dprintk(verbose, MB86A16_DEBUG, 1, "mb86a16_init"); + return 0; +} + +static int mb86a16_sleep(struct dvb_frontend *fe) +{ + return 0; +} + +static int mb86a16_read_signal_strength(struct dvb_frontend *fe, u16 *strength) +{ + struct mb86a16_state* state = fe->demodulator_priv; + u8 tmp; + s32 signal; + + mb86a16_read(state, 0x15, &tmp); + signal= 0xffff - tmp; + signal = signal * 5 / 8; + *strength = (signal > 0xffff) ? 0xffff : (signal < 0) ? 0 : signal; + + return 0; +} + +static int mb86a16_read_snr(struct dvb_frontend *fe, u16 *snr) +{ + struct mb86a16_state* state = fe->demodulator_priv; + u8 tmp; + s32 xsnr; + + mb86a16_read(state, 0x26, &tmp); + xsnr = 0xff00 + tmp; + *snr = xsnr; + + return 0; +} + +static struct dvb_frontend_ops mb86a16_ops = { + .info = { + .name = "Fujitsu MB86A16 DVB-S", + .type = FE_QPSK, + .frequency_min = 950000, + .frequency_max = 2150000, + .frequency_stepsize = 125, + .frequency_tolerance = 0, + .symbol_rate_min = 1000000, + .symbol_rate_max = 45000000, + .symbol_rate_tolerance = 500, + .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | + FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | + FE_CAN_FEC_7_8 | FE_CAN_QPSK | + FE_CAN_FEC_AUTO + }, + .release = mb86a16_release, + .tune = mb86a16_set_frontend, + .get_frontend_algo = mb86a16_frontend_algo, + .init = mb86a16_init, + .sleep = mb86a16_sleep, + + .diseqc_send_master_cmd = mb86a16_send_diseqc_msg, + .diseqc_send_burst = mb86a16_send_diseqc_burst, + .set_tone = mb86a16_send_tone_msg, + + .read_status = mb86a16_read_status, + .read_signal_strength = mb86a16_read_signal_strength, + .read_snr = mb86a16_read_snr, +}; + +struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config, + struct i2c_adapter *i2c_adap) +{ + u8 dev_id = 0; + struct mb86a16_state *state = NULL; + + state = kmalloc(sizeof (struct mb86a16_state), GFP_KERNEL); + if (state == NULL) + goto error; + + state->config = config; + state->i2c_adap = i2c_adap; + + mb86a16_read(state, 0x7f, &dev_id); + if (dev_id != 0xfe) + goto error; + + memcpy(&state->frontend.ops, &mb86a16_ops, sizeof (struct dvb_frontend_ops)); + state->frontend.demodulator_priv = state; + state->frontend.ops.set_voltage = state->config->set_voltage; + + return &state->frontend; +error: + kfree(state); + return NULL; +} + +MODULE_LICENSE("GPL"); +EXPORT_SYMBOL(mb86a16_attach); + diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/frontends/mb86a16.h kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/mb86a16.h --- kernel-2.6.24.4-orig/drivers/media/dvb/frontends/mb86a16.h 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/mb86a16.h 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,37 @@ +/* + Mantis PCI bridge driver + + Copyright (C) 2005, 2006 Manu Abraham (abraham.manu@gmail.com) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#ifndef __MB86A16_H +#define __MB86A16_H + +#include +#include "dvb_frontend.h" + + +struct mb86a16_config { + u8 demod_address; + int (*set_voltage)(struct dvb_frontend *fe, fe_sec_voltage_t voltage); +}; + +extern struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config, + struct i2c_adapter *i2c_adap); + + +#endif //__MB86A16_H diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/frontends/stb0899_chip.c kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/stb0899_chip.c --- kernel-2.6.24.4-orig/drivers/media/dvb/frontends/stb0899_chip.c 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/stb0899_chip.c 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,870 @@ + +#include +#include + +#include "dvb_frontend.h" +#include "stb0899_chip.h" + +typedef struct node +{ + STCHIP_Handle_t hChip; + struct node *pNextNode; +}NODE; + +static NODE *pFirstNode = NULL; + +static u32 LastBaseAdress=0xffffffff; +static u16 LastPointer=0xffff; + +extern int debug; + +/******************************************************************************* + **FUNCTION :: I2cWrite + **ACTION :: Write data to the slave + **PARAMS IN :: hChip ==> Handle to the chip + ** NbData ==> Number of data to write/read + ** Data ==> buffer containing data which will be writen + **PARAMS OUT:: NONE + **RETURN :: if success return ret else EREMOTEIO + ********************************************************************************/ +int I2cWrite(STCHIP_Handle_t hChip, u8 *Data, u8 NbData) +{ + int ret; + + struct i2c_msg msg = { + .addr = hChip->I2cAddr, + .flags = 0, + .buf = Data, + .len = NbData + }; + + ret = i2c_transfer(hChip->I2c_adap, &msg, 1); + if (ret != 1) { + dprintk("I2cWrite Error"); + return -EREMOTEIO; + } else { + //dprintk("I2cWrite successful\n"); + + return ret; + } + return -EIO; +} + +/******************************************************************************* + **FUNCTION :: I2cRead + **ACTION :: Read data from the slave + **PARAMS IN :: hChip ==> Handle to the chip + ** NbData ==> Number of data to write/read + **PARAMS OUT:: Data ==> Buffer containing data readed + **RETURN :: if success return ret else EREMOTEIO + ********************************************************************************/ +int I2cRead(STCHIP_Handle_t hChip, u8 *Data, u8 NbData) +{ + int ret; + + struct i2c_msg msg = { + .addr = hChip->I2cAddr, + .flags = I2C_M_RD, + .buf = Data, + .len = NbData + }; + + ret = i2c_transfer(hChip->I2c_adap, &msg, 1); + if (ret != 1) { + dprintk("I2cRead Error"); + return -EREMOTEIO; + } else { + //dprintk("I2cRead successful"); + return ret; + } + return -EIO; + } + +/* List routines*/ +static NODE *AppendNode(STCHIP_Handle_t hChip) +{ + NODE *pNode = pFirstNode; + + if(pNode == NULL) + { /* Allocation of the first node*/ + pNode = (NODE *)kmalloc(sizeof(NODE), GFP_KERNEL); + pFirstNode = pNode; + } + else + { /* Allocation of a new node */ + while(pNode->pNextNode != NULL) /* Search of the last node*/ + pNode = pNode->pNextNode; + + /* Memory allocation */ + pNode->pNextNode = (NODE *)kmalloc(sizeof(NODE),GFP_KERNEL); + + if(pNode->pNextNode != NULL) /* Check allocation */ + pNode = pNode->pNextNode; + else + pNode = NULL; + } + + if(pNode != NULL) /* if allocation ok */ + { + /* Fill the node */ + pNode->hChip = hChip; + pNode->pNextNode = NULL; + } + + return pNode; +} + +/***************************************************** +**FUNCTION :: ChipGetFirst +**ACTION :: Retrieve the first chip handle +**PARAMS IN :: NONE +**PARAMS OUT :: NONE +**RETURN :: STCHIP_Handle_t if ok, NULL otherwise +*****************************************************/ +static STCHIP_Handle_t ChipGetFirst(void) +{ + if((pFirstNode != NULL) && (pFirstNode->hChip != NULL)) + return pFirstNode->hChip; + else + return NULL; +} + +/***************************************************** +**FUNCTION :: ChipFindNode +**ACTION :: Find that node that contains the chip +**PARAMS IN :: NONE +**PARAMS OUT :: NONE +**RETURN :: STCHIP_Handle_t if ok, NULL otherwise +*****************************************************/ +static NODE *ChipFindNode(STCHIP_Handle_t hChip) +{ + NODE *pNode = pFirstNode; + + if(pNode != NULL) + { + while((pNode->hChip != hChip) && (pNode->pNextNode != NULL)) + pNode = pNode->pNextNode; + + if(pNode->hChip != hChip) + pNode = NULL; + } + + return pNode; +} + +/***************************************************** +**FUNCTION :: ChipGetNext +**ACTION :: Retrieve the handle of the next chip +**PARAMS IN :: hPrevChip==> handle of the previous chip +**PARAMS OUT :: NONE +**RETURN :: STCHIP_Handle_t if ok, NULL otherwise +*****************************************************/ +static STCHIP_Handle_t ChipGetNext(STCHIP_Handle_t hPrevChip) +{ + NODE *pNode; + + pNode = ChipFindNode(hPrevChip); + if((pNode != NULL) && (pNode->pNextNode != NULL)) + return pNode->pNextNode->hChip; + else + return NULL; +} + +/***************************************************** +**FUNCTION :: ChipGetHandleFromName +**ACTION :: Retrieve the handle of chip with its name +**PARAMS IN :: Name ==> name of the chip +**PARAMS OUT :: NONE +**RETURN :: STCHIP_Handle_t if ok, NULL otherwise +*****************************************************/ +static STCHIP_Handle_t ChipGetHandleFromName(char *Name) +{ + STCHIP_Handle_t hChip; + + hChip = ChipGetFirst(); + while((hChip != NULL) && (strcmp(hChip->Name,Name) != 0)) + { + hChip = ChipGetNext(hChip); + } + + return hChip; +} + +/***************************************************** +**FUNCTION :: ChipOpen +**ACTION :: Open a new chip +**PARAMS IN :: Name ==> Name of the chip +** I2cAddr ==> I2C address of the chip +** NbRegs ==> number of register in the chip +** NbFields==> number of field in the chip +**PARAMS OUT :: NONE +**RETURN :: Handle to the chip, NULL if an error occur +*****************************************************/ +STCHIP_Handle_t ChipOpen(STCHIP_Info_t *hChipOpenParams) +{ + STCHIP_Handle_t hChip; + + /* Allocation of the chip structure */ + hChip = (STCHIP_Handle_t)kmalloc(sizeof(STCHIP_Info_t), GFP_KERNEL); + + if((hChip != NULL) && (hChipOpenParams != NULL)) + { + /* Allocation of the register map*/ + hChip->pRegMap = (STCHIP_Register_t *)kmalloc(hChipOpenParams->NbRegs*sizeof(STCHIP_Register_t), GFP_KERNEL); + + if(hChip->pRegMap != NULL) + { + /* Allocation of the field map*/ + hChip->pFieldMap = (STCHIP_Field_t *)kmalloc(hChipOpenParams->NbFields*sizeof(STCHIP_Field_t), GFP_KERNEL); + + if(hChip->pFieldMap != NULL) + { + STCHIP_Handle_t hhChip; + NODE *pNode = NULL; + + hhChip = ChipGetHandleFromName(hChipOpenParams->Name); + + if(hhChip==NULL) + pNode = AppendNode(hChip); + + if ((hhChip==NULL) && (pNode==NULL)) + { + kfree(hChip->pFieldMap); + kfree(hChip->pRegMap); + kfree(hChip); + hChip = NULL; + } + else + { + hChip->I2cAddr = hChipOpenParams->I2cAddr; + hChip->I2c_adap = hChipOpenParams->I2c_adap; + strcpy(hChip->Name,hChipOpenParams->Name); + hChip->NbRegs = hChipOpenParams->NbRegs; + hChip->NbFields = hChipOpenParams->NbFields; + hChip->ChipMode = hChipOpenParams->ChipMode; + hChip->Repeater = hChipOpenParams->Repeater; + hChip->RepeaterHost = hChipOpenParams->RepeaterHost; + hChip->RepeaterFn = hChipOpenParams->RepeaterFn; + hChip->WrStart = hChipOpenParams->WrStart; + hChip->WrSize = hChipOpenParams->WrSize; + hChip->RdStart = hChipOpenParams->RdStart; + hChip->RdSize = hChipOpenParams->RdSize; + hChip->ChipError = CHIPERR_NO_ERROR; + } + } + else + { + kfree(hChip->pRegMap); + kfree(hChip); + hChip = NULL; + } + } + else + { + kfree(hChip); + hChip = NULL; + } + } + return hChip; +} + +/***************************************************** +**FUNCTION :: ChipAddReg +**ACTION :: Add a new register to the register map +**PARAMS IN :: hChip ==> Handle to the chip +** Id ==> Id of the register +** Name ==> Name of the register +** Address ==> I2C address of the register +** Default ==> Default value of the register +**PARAMS OUT :: NONE +**RETURN :: Error +*****************************************************/ +STCHIP_Error_t ChipAddReg(STCHIP_Handle_t hChip, STCHIP_RegSize_t Size, u16 RegId, char * Name, u16 Address, u32 Default, STCHIP_Access_t Access, STCHIP_Pointed_t Pointed, u16 PointerRegAddr, u32 BaseAdress) +{ + STCHIP_Register_t *pReg; + + if(hChip != NULL) + { + //if((RegId >= 0) && (RegId < hChip->NbRegs)) + if (RegId < hChip->NbRegs) + { + pReg = &hChip->pRegMap[RegId]; + + pReg->Addr = Address; + pReg->Size = Size; + pReg->Default = Default; + pReg->Value = Default; + pReg->Access = Access; + strcpy(pReg->Name, Name); + pReg->Pointed = Pointed; + pReg->PointerRegAddr = PointerRegAddr; + pReg->BaseAdress = BaseAdress; + } + else + { + hChip->ChipError = CHIPERR_INVALID_REG_ID; + } + } + else + return CHIPERR_INVALID_HANDLE; + + return hChip->ChipError; +} + +/***************************************************** +**FUNCTION :: CreateMask +**ACTION :: Create a mask according to its number of bits and position +**PARAMS IN :: field ==> Id of the field +**PARAMS OUT :: NONE +**RETURN :: mask of the field +*****************************************************/ +static u32 CreateMask(char NbBits, char Pos) +{ + int i; + u32 mask=0; + + /*Create mask*/ + for (i = 0; i < NbBits; i++) + { + mask <<= 1 ; + mask += 1 ; + } + mask = mask << Pos; + + return mask; +} + +/***************************************************** +**FUNCTION :: ChipAddField +**ACTION :: Add a field to the field map +**PARAMS IN :: hChip ==> Handle to the chip +** RegId ==> Id of the register which contains the field +** FieldId ==> Id of the field +** Name ==> Name of the field +** Pos ==> Position (number of left shifts from LSB position) in the register +** NbBits ==> Size (in bits) of the field +** Type ==> SIGNED or UNSIGNED +**PARAMS OUT :: NONE +**RETURN :: Error +*****************************************************/ +STCHIP_Error_t ChipAddField(STCHIP_Handle_t hChip, u16 RegId, u32 FieldId, char * Name, char Pos, char NbBits, STCHIP_FieldType_t Type) +{ + STCHIP_Field_t *pField; + + if(hChip != NULL) + { + if(RegId < hChip->NbRegs) + { + if(FieldId < (u32)(hChip->NbFields)) + { + pField = &hChip->pFieldMap[FieldId]; + + strcpy(pField->Name, Name); + pField->Reg = RegId; + pField->Pos = Pos; + pField->Bits = NbBits; + pField->Type = Type; + if(NbBits) + pField->Mask = CreateMask(NbBits,Pos); + else + hChip->ChipError = CHIPERR_INVALID_FIELD_SIZE; + } + else + hChip->ChipError = CHIPERR_INVALID_FIELD_ID; + } + else + { + hChip->ChipError = CHIPERR_INVALID_REG_ID; + } + } + else + return CHIPERR_INVALID_HANDLE; + + return hChip->ChipError; +} + +/***************************************************** +**FUNCTION :: ChipSetOneRegister +**ACTION :: Set the value of one register +**PARAMS IN :: hChip ==> Handle to the chip +** reg_id ==> Id of the register +** Data ==> Data to store in the register +**PARAMS OUT :: NONE +**RETURN :: Error +*****************************************************/ +STCHIP_Error_t ChipSetOneRegister(STCHIP_Handle_t hChip,u16 RegId,u32 Data) +{ + if(hChip) + { + if(RegId < hChip->NbRegs) + { + if(hChip->pRegMap[RegId].Access != STCHIP_ACCESS_R) + { + hChip->pRegMap[RegId].Value = Data; + + if(hChip->ChipMode != STCHIP_MODE_NOSUBADR) + ChipSetRegisters(hChip, RegId, 1); + else + ChipSetRegisters(hChip, hChip->WrStart, hChip->WrSize); + } + } + else + { + hChip->ChipError = CHIPERR_INVALID_REG_ID; + } + } + else + return CHIPERR_INVALID_HANDLE; + + return hChip->ChipError; +} + +/***************************************************** +**FUNCTION :: ChipGetOneRegister +**ACTION :: Get the value of one register +**PARAMS IN :: hChip ==> Handle to the chip +** reg_id ==> Id of the register +**PARAMS OUT:: NONE +**RETURN :: Register's value +*****************************************************/ +int ChipGetOneRegister(STCHIP_Handle_t hChip, u16 RegId) +{ + u32 data = 0xFFFFFFFF; + + if(hChip) + { + if((hChip->ChipMode != STCHIP_MODE_NOSUBADR) && (hChip->ChipMode != STCHIP_MODE_NO_R_SUBADR)) + { + if(ChipGetRegisters(hChip,RegId,1) == CHIPERR_NO_ERROR) + data = hChip->pRegMap[RegId].Value; + } + else + { + if(ChipGetRegisters(hChip, hChip->RdStart, hChip->RdSize) == CHIPERR_NO_ERROR) + data = hChip->pRegMap[RegId].Value; + } + } + + return data; +} + +/***************************************************** +**FUNCTION :: ChipSetRegisters +**ACTION :: Set values of consecutive's registers (values are taken in RegMap) +**PARAMS IN :: hChip==> Handle to the chip +** FirstReg==> Id of the first register +** NbRegs ==> Number of register to write +**PARAMS OUT :: NONE +**RETURN :: Error +*****************************************************/ +STCHIP_Error_t ChipSetRegisters(STCHIP_Handle_t hChip, int FirstReg, int NbRegs) +{ + unsigned char data[100],nbdata = 0; + int i,j; + //printk(KERN_ERR "ChipSetRegisters--->\n"); + if(hChip) + { + if(!hChip->ChipError) + { + if(NbRegs < 20) + { + if((FirstReg >= 0) && ((FirstReg + NbRegs - 1) < hChip->NbRegs)) + { + if(hChip->pRegMap[FirstReg].Pointed == STCHIP_POINTED) + { + if((hChip->pRegMap[FirstReg].PointerRegAddr != LastPointer) || (hChip->pRegMap[FirstReg].BaseAdress != LastBaseAdress)) + { + /* Write pointer register (4x8bits read access) */ + nbdata=0; + data[nbdata++] = MSB(hChip->pRegMap[FirstReg].PointerRegAddr); + data[nbdata++] = LSB(hChip->pRegMap[FirstReg].PointerRegAddr); + + for(i=0;i<4;i++) + data[nbdata++] = (unsigned char)((hChip->pRegMap[FirstReg].BaseAdress>>(8*i))&0xFF); + /* write base adress value */ + if((I2cWrite(hChip,data,nbdata)) < 0) + hChip->ChipError = CHIPERR_I2C_NO_ACK; + + LastPointer = hChip->pRegMap[FirstReg].PointerRegAddr; + LastBaseAdress = hChip->pRegMap[FirstReg].BaseAdress; + } + /* Write pointed register (4x8bits read access) */ + nbdata = 0; + data[nbdata++] = MSB(hChip->pRegMap[FirstReg].Addr); + data[nbdata++] = LSB(hChip->pRegMap[FirstReg].Addr); + + for(j=0; jpRegMap[FirstReg+j].Value>>(8*i))&0xFF); + /* write base adress value */ + if(I2cWrite(hChip, data, nbdata) < 0) + hChip->ChipError = CHIPERR_I2C_NO_ACK; + } + else + { + nbdata = 0; + switch(hChip->ChipMode) + { + case STCHIP_MODE_SUBADR_16: + data[nbdata++] = MSB(hChip->pRegMap[FirstReg].Addr); + case STCHIP_MODE_SUBADR_8: + case STCHIP_MODE_NO_R_SUBADR: + data[nbdata++] = LSB(hChip->pRegMap[FirstReg].Addr); + case STCHIP_MODE_NOSUBADR: + for(i=0;ipRegMap[FirstReg+i].Value)&0xFF); + break; + } + + if(hChip->Repeater) + hChip->RepeaterFn(hChip->RepeaterHost, TRUE); + + //msleep(1); + + if(I2cWrite(hChip,data,nbdata) < 0) + { + hChip->ChipError = CHIPERR_I2C_NO_ACK; + } + + if(hChip->Repeater) + hChip->RepeaterFn(hChip->RepeaterHost,FALSE); + } + } + else + { + hChip->ChipError = CHIPERR_INVALID_REG_ID; + } + } + else + hChip->ChipError = CHIPERR_I2C_BURST; + } + } + else + return CHIPERR_INVALID_HANDLE; + //printk(KERN_ERR "ChipSetRegisters<---\n"); + return hChip->ChipError; +} + +/***************************************************** +**FUNCTION :: ChipGetRegisters +**ACTION :: Get values of consecutive's registers (values are writen in RegMap) +**PARAMS IN :: hChip ==> Handle to the chip +** FirstReg==> Id of the first register +** NbRegs ==> Number of register to read +**PARAMS OUT :: NONE +**RETURN :: Error +*****************************************************/ +STCHIP_Error_t ChipGetRegisters(STCHIP_Handle_t hChip, int FirstReg, int NbRegs) +{ + u8 data[100],dataread[100],dummy[4],nbdata =0; + u16 address; + u8 dum; + int i,j=0; + + if(hChip) + { + if(!hChip->ChipError) + { + if(NbRegs < 20) + { + if((FirstReg >= 0) && ((FirstReg + NbRegs - 1) < hChip->NbRegs)) + { + if(hChip->pRegMap[FirstReg].Pointed == STCHIP_POINTED) + { + if((hChip->pRegMap[FirstReg].PointerRegAddr != LastPointer) || (hChip->pRegMap[FirstReg].BaseAdress != LastBaseAdress)) + { + /* Write pointer register (4x8bits write access) */ + nbdata = 0; + data[nbdata++] = MSB(hChip->pRegMap[FirstReg].PointerRegAddr); + data[nbdata++] = LSB(hChip->pRegMap[FirstReg].PointerRegAddr); + + for(i=0; i<4; i++) + data[nbdata++] = (unsigned char)((hChip->pRegMap[FirstReg].BaseAdress>>(8*i))&0xFF); + + if(I2cWrite(hChip,data,nbdata) < 0) + hChip->ChipError = CHIPERR_I2C_NO_ACK; + + LastPointer = hChip->pRegMap[FirstReg].PointerRegAddr; + LastBaseAdress = hChip->pRegMap[FirstReg].BaseAdress; + } + nbdata = 0; + if((LSB(hChip->pRegMap[FirstReg].Addr) & 0x08) == 0) + dum = 0x20; + else + dum = 0; + dummy[nbdata++] = MSB(hChip->pRegMap[FirstReg].Addr); + dummy[nbdata++] = dum; + /* write register adress+20 value */ + if(I2cWrite(hChip, dummy, nbdata) < 0) + hChip->ChipError = CHIPERR_I2C_NO_ACK; + + if(I2cRead(hChip,dummy,4) < 0) + hChip->ChipError = CHIPERR_I2C_NO_ACK; + + /* Read pointed register (4x8bits read access) */ + nbdata = 0; + address = hChip->pRegMap[FirstReg].Addr; + data[nbdata++] = MSB(address); + data[nbdata++] = LSB(address); + + if(I2cWrite(hChip,data,nbdata) < 0) + hChip->ChipError = CHIPERR_I2C_NO_ACK; + + if(I2cRead(hChip,dataread,(4*NbRegs)) < 0) + hChip->ChipError = CHIPERR_I2C_NO_ACK; + memcpy(data, dataread, (4*NbRegs)); + } + else + { + nbdata = 0; + switch(hChip->ChipMode) + { + case STCHIP_MODE_SUBADR_16: + data[nbdata++] = MSB(hChip->pRegMap[FirstReg].Addr); + case STCHIP_MODE_SUBADR_8: + data[nbdata++]=LSB(hChip->pRegMap[FirstReg].Addr); + + if(hChip->Repeater) + hChip->RepeaterFn(hChip->RepeaterHost, TRUE); + /* Write sub address */ + if(I2cWrite(hChip,data,nbdata) < 0) + hChip->ChipError = CHIPERR_I2C_NO_ACK; + + if(hChip->Repeater) + hChip->RepeaterFn(hChip->RepeaterHost, FALSE); + + case STCHIP_MODE_NOSUBADR: + case STCHIP_MODE_NO_R_SUBADR: + if(hChip->Repeater) + hChip->RepeaterFn(hChip->RepeaterHost, TRUE); + + nbdata = 0; + if(hChip->pRegMap[FirstReg].Pointed == STCHIP_POINTED) + for(i=0; iChipError = CHIPERR_I2C_NO_ACK; + + if(hChip->Repeater) + hChip->RepeaterFn(hChip->RepeaterHost, FALSE); + + /*only for inbuf and packet delin registers*/ + if((MSB(hChip->pRegMap[FirstReg].Addr) == 0xf6) || (MSB(hChip->pRegMap[FirstReg].Addr) == 0xf2)) + { + dummy[0] = MSB(hChip->pRegMap[FirstReg].Addr); + dummy[1] = 0xff; + + if(I2cWrite(hChip,dummy,2) < 0) + hChip->ChipError = CHIPERR_I2C_NO_ACK; + + if(I2cRead(hChip,dummy,1) < 0) + hChip->ChipError = CHIPERR_I2C_NO_ACK; + } + break; + } + } + /*Update RegMap structure */ + for(i=0; iChipError) + { + hChip->pRegMap[FirstReg+i].Value = data[j++]; + + if(hChip->pRegMap[FirstReg+i].Size >= STCHIP_REG_16) + hChip->pRegMap[FirstReg+i].Value += data[j++]<<8; + + if(hChip->pRegMap[FirstReg+i].Size >= STCHIP_REG_24) + hChip->pRegMap[FirstReg+i].Value += data[j++]<<16; + + if(hChip->pRegMap[FirstReg+i].Size >= STCHIP_REG_32) + hChip->pRegMap[FirstReg+i].Value += data[j++]<<24; + } + else + hChip->pRegMap[FirstReg+i].Value = 0xFFFFFFFF; + } + else + { + hChip->ChipError = CHIPERR_INVALID_REG_ID; + } + } + else + hChip->ChipError = CHIPERR_I2C_BURST; + } + } + else + return CHIPERR_INVALID_HANDLE; + + return hChip->ChipError; +} + +/***************************************************** +**FUNCTION :: ChipSetFieldImage +**ACTION :: Set value of a field in RegMap +**PARAMS IN :: hChip ==> Handle to the chip +** FieldId ==> Id of the field +** Value ==> Value of the field +**PARAMS OUT :: NONE +**RETURN :: Error +*****************************************************/ +STCHIP_Error_t ChipSetFieldImage(STCHIP_Handle_t hChip, u32 FieldId, int Value) +{ + STCHIP_Field_t *pfield; + + if(hChip != NULL) + { + if(!hChip->ChipError) + { + if(FieldId < (u32)(hChip->NbFields)) + { + pfield = &hChip->pFieldMap[FieldId]; + + if(pfield->Type == CHIP_SIGNED) + /*compute signed fieldval*/ + Value = (Value > 0 ) ? Value : Value + (1<Bits); + + /*Shift and mask value*/ + Value = pfield->Mask & (Value << pfield->Pos); + /*Concat register value and fieldval*/ + hChip->pRegMap[pfield->Reg].Value = (hChip->pRegMap[pfield->Reg].Value & (~pfield->Mask)) + Value; + } + else + hChip->ChipError = CHIPERR_INVALID_FIELD_ID; + } + } + else + return CHIPERR_INVALID_HANDLE; + + return hChip->ChipError; +} + +/***************************************************** +**FUNCTION :: ChipSetField +**ACTION :: Set value of a field in the chip +**PARAMS IN :: hChip ==> Handle to the chip +** FieldId ==> Id of the field +** Value ==> Value to write +**PARAMS OUT :: NONE +**RETURN :: Error +*****************************************************/ +STCHIP_Error_t ChipSetField(STCHIP_Handle_t hChip, u32 FieldId, int Value) +{ + STCHIP_Field_t *pfield; + + if(hChip) + { + if(!hChip->ChipError) + { + if(FieldId < (u32)(hChip->NbFields)) + { + /*Just for code simplification*/ + pfield = &hChip->pFieldMap[FieldId]; + /*Read the register*/ + ChipGetOneRegister(hChip,pfield->Reg); + /*Compute new RegMap value */ + ChipSetFieldImage(hChip,FieldId,Value); + /*Write the register */ + ChipSetOneRegister(hChip, pfield->Reg, hChip->pRegMap[pfield->Reg].Value); + } + else + hChip->ChipError = CHIPERR_INVALID_FIELD_ID; + } + } + else + return CHIPERR_INVALID_HANDLE; + + return hChip->ChipError; +} + +/***************************************************** +**FUNCTION :: ChipGetFieldImage +**ACTION :: get the value of a field from RegMap +**PARAMS IN :: hChip ==> Handle of the chip +** FieldId ==> Id of the field +**PARAMS OUT :: NONE +**RETURN :: field's value +*****************************************************/ +int ChipGetFieldImage(STCHIP_Handle_t hChip, u32 FieldId) +{ + int value = 0xFFFFFFFF; + STCHIP_Field_t *pfield; + + if(hChip) + { + if(FieldId < (u32)(hChip->NbFields)) + { + pfield = &hChip->pFieldMap[FieldId]; + if(!hChip->ChipError) + value = hChip->pRegMap[pfield->Reg].Value; + + value = (value & pfield->Mask) >> pfield->Pos; /*Extract field*/ + + if((pfield->Type == CHIP_SIGNED) && (value & (1 << (pfield->Bits-1)))) + value = value - (1<Bits);/*Compute signed value*/ + } + else + hChip->ChipError = CHIPERR_INVALID_FIELD_ID; + } + + return value; +} + +/***************************************************** +**FUNCTION :: ChipGetField +**ACTION :: get the value of a field from the chip +**PARAMS IN :: hChip ==> Handle of the chip +** FieldId ==> Id of the field +**PARAMS OUT :: NONE +**RETURN :: field's value +*****************************************************/ +int ChipGetField(STCHIP_Handle_t hChip,u32 FieldId) +{ + int value = 0xFFFFFFFF; + + if(hChip) + { + if(FieldId < (u32)(hChip->NbFields)) + { + ChipGetOneRegister(hChip, hChip->pFieldMap[FieldId].Reg); + value = ChipGetFieldImage(hChip, FieldId); + } + else + hChip->ChipError = CHIPERR_INVALID_FIELD_ID; + } + + return value; +} + +/***************************************************** +**FUNCTION :: ChipApplyDefaultValues +**ACTION :: Write default values in all the registers +**PARAMS IN :: hChip ==> Handle of the chip +**PARAMS OUT :: NONE +**RETURN :: Error +*****************************************************/ +STCHIP_Error_t ChipApplyDefaultValues(STCHIP_Handle_t hChip) +{ + int reg = 0; + + if(hChip != NULL) + { + if(hChip->ChipMode != STCHIP_MODE_NOSUBADR) + { + while((!hChip->ChipError) && (reg < hChip->NbRegs)) + { + ChipSetOneRegister(hChip,(u16)reg,hChip->pRegMap[reg].Default); + reg++; + } + } + else + { printk(KERN_ERR "hChip->ChipMode == STCHIP_MODE_NOSUBADR\n"); + ChipSetOneRegister(hChip,(u16)reg,hChip->pRegMap[reg].Default); + } + } + else + return CHIPERR_INVALID_HANDLE; + + return hChip->ChipError; +} + diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/frontends/stb0899_chip.h kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/stb0899_chip.h --- kernel-2.6.24.4-orig/drivers/media/dvb/frontends/stb0899_chip.h 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/stb0899_chip.h 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,180 @@ +/* ------------------------------------------------------------------------- +File Name: stn0899_chip.h + +Description: Present a register based interface to hardware connected on an I2C bus. + +Copyright (C) 1999-2001 STMicroelectronics + +History: + date: 10-October-2001 +version: 1.0.0 + author: SA +comment: STAPIfied by GP + +---------------------------------------------------------------------------- */ + +/* define to prevent recursive inclusion */ +#ifndef STB0899_CHIP_H +#define STB0899_CHIP_H + +#include "stb0899_common.h" +#include +#include "dvb_frontend.h" + + +/* enumerations------------------------------------------------------------- */ + +/* access modes for fields and registers */ +typedef enum +{ + STCHIP_ACCESS_WR, /* can be read and written */ + STCHIP_ACCESS_R, /* only be read from */ + STCHIP_ACCESS_W, /* only be written to */ + STCHIP_ACCESS_NON /* cannot be read or written (guarded register, e.g. register skipped by ChipApplyDefaultValues() etc.) */ +} +STCHIP_Access_t; + +/* register field type */ +typedef enum +{ + CHIP_UNSIGNED, + CHIP_SIGNED +} +STCHIP_FieldType_t; + +/* error codes */ +typedef enum +{ + CHIPERR_NO_ERROR = 0, /* 0 No error encountered */ + CHIPERR_INVALID_HANDLE, /* 1 Using of an invalid chip handle */ + CHIPERR_INVALID_REG_ID, /* 2 Using of an invalid register */ + CHIPERR_INVALID_FIELD_ID, /* 3 Using of an Invalid field */ + CHIPERR_INVALID_FIELD_SIZE, /* 4 Using of a field with an invalid size */ + CHIPERR_I2C_NO_ACK, /* 5 No acknowledge from the chip */ + CHIPERR_I2C_BURST /* 6 Two many registers accessed in burst mode */ +} +STCHIP_Error_t; + +/* how to access I2C bus */ +typedef enum +{ + STCHIP_MODE_SUBADR_8, /* (e.g. demod chip) */ + STCHIP_MODE_SUBADR_16, /* (e.g. demod chip) */ + STCHIP_MODE_NOSUBADR, /* | (e.g. tuner chip) */ + STCHIP_MODE_NO_R_SUBADR +} +STCHIP_Mode_t; + +typedef enum +{ + STCHIP_REG_8, + STCHIP_REG_16, + STCHIP_REG_24, + STCHIP_REG_32 +}STCHIP_RegSize_t; + +typedef enum +{ + STCHIP_NOT_POINTED=0, + STCHIP_POINTED +}STCHIP_Pointed_t; + +/* structures ---------------------------- +---------------------------------- */ + +/* register information */ +typedef struct +{ + u16 Addr; /* Address */ + STCHIP_RegSize_t Size; /* Register size in Byte*/ + u32 Default; /* Default value */ + u32 Value; /* Current value */ + char Name[30]; /* Name */ + STCHIP_Access_t Access; /* access mode */ + STCHIP_Pointed_t Pointed; /* Register Pointed or not*/ + u16 PointerRegAddr; /* Pointer Adress*/ + u32 BaseAdress; /* Base Adress*/ +} +STCHIP_Register_t; + +/* register field information */ +typedef struct +{ + u16 Reg; /* Register index */ + unsigned char Pos; /* Bit position */ + unsigned char Bits; /* Bit width */ + u32 Mask; /* Mask compute with width and position */ + STCHIP_FieldType_t Type; /* Signed or unsigned */ + char Name[30]; /* Name */ +} +STCHIP_Field_t; + +/* data about a specific chip */ +typedef struct stchip_Info_t +{ + unsigned char I2cAddr; /* Chip I2C address */ + struct i2c_adapter *I2c_adap; + char Name[30]; /* Name of the chip */ + int NbRegs; /* Number of registers in the chip */ + int NbFields; /* Number of fields in the chip */ + STCHIP_Register_t *pRegMap; /* Pointer to register map */ + STCHIP_Field_t *pFieldMap; /* Pointer to field map */ + STCHIP_Error_t ChipError; /* Error state */ + STCHIP_Mode_t ChipMode; /* Access bus in demod (SubAdr) or tuner (NoSubAdr) mode */ + +#ifdef HOST_PC /* PC specific parameters */ + BOOL Repeater; /* Is repeater enabled or not ? */ + /* Owner of the repeater */ + struct stchip_Info_t *RepeaterHost; + /* Pointer to repeater routine */ + STCHIP_Error_t (*RepeaterFn)(struct stchip_Info_t *hChip,BOOL State); + + /* Parameters needed for non sub address devices */ + u32 WrStart; /* Id of the first writable register */ + u32 WrSize; /* Number of writable registers */ + u32 RdStart; /* Id of the first readable register */ + u32 RdSize; /* Number of readable registers */ +#endif +} +STCHIP_Info_t; + +/* Handle to a chip */ +typedef STCHIP_Info_t *STCHIP_Handle_t; + +/* Pointer to repeater routine */ +typedef STCHIP_Error_t (*STCHIP_RepeaterFn_t)(STCHIP_Handle_t hChip,BOOL State); + +/* functions --------------------------------------------------------------- */ + +/* Creation and destruction routines */ +STCHIP_Handle_t ChipOpen(STCHIP_Info_t *hChipOpenParams); + +STCHIP_Error_t ChipAddReg(STCHIP_Handle_t hChip, STCHIP_RegSize_t Size, u16 RegId, char * Name, u16 Address, u32 Default, STCHIP_Access_t Access, STCHIP_Pointed_t Pointed, u16 PointerRegAddr, u32 BaseAdress); + +STCHIP_Error_t ChipAddField(STCHIP_Handle_t hChip, u16 RegId, u32 FieldId, char *Name, char Pos, char NbBits, STCHIP_FieldType_t Type); + +/* Utility routines */ +STCHIP_Error_t ChipApplyDefaultValues(STCHIP_Handle_t hChip); + +/* Access routines */ +int I2cWrite(STCHIP_Handle_t hChip, u8 *Data, u8 NbData); +int I2cRead(STCHIP_Handle_t hChip, u8 *Data, u8 NbData); + +STCHIP_Error_t ChipSetOneRegister(STCHIP_Handle_t hChip, u16 RegId, u32 Data); +int ChipGetOneRegister(STCHIP_Handle_t hChip, u16 RegId); + +STCHIP_Error_t ChipSetRegisters(STCHIP_Handle_t hChip, int FirstReg, int NbRegs); +STCHIP_Error_t ChipGetRegisters(STCHIP_Handle_t hChip, int FirstReg, int NbRegs); + +STCHIP_Error_t ChipSetField(STCHIP_Handle_t hChip, u32 FieldId, int Value); +int ChipGetField(STCHIP_Handle_t hChip, u32 FieldId); + +STCHIP_Error_t ChipSetFieldImage(STCHIP_Handle_t hChip, u32 FieldId, int Value); +int ChipGetFieldImage(STCHIP_Handle_t hChip, u32 FieldId); + + + +#endif + + + diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/frontends/stb0899_common.h kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/stb0899_common.h --- kernel-2.6.24.4-orig/drivers/media/dvb/frontends/stb0899_common.h 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/stb0899_common.h 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,50 @@ + +#ifndef STB0899_COMMON_H +#define STB0899_COMMON_H + + +#define HOST_PC +#define NO_GUI + +#define I2C_WRITE 0 +#define I2C_READ 1 + +#ifndef NULL +#define NULL (void *)0 +#endif + +/* BOOL type constant values */ +#ifndef TRUE + #define TRUE (1 == 1) +#endif +#ifndef FALSE + #define FALSE (!TRUE) +#endif + +#define INRANGE(X,Y,Z) (((X<=Y) && (Y<=Z))||((Z<=Y) && (Y<=X)) ? 1 : 0) +#define LSB(X) ((X & 0xFF)) +#define MSB(Y) ((Y>>8)& 0xFF) +#define ABS(X) ((X)<0?(-X):(X)) +#define MAKEWORD(X,Y) ((((X)&0xFF)<<8)+((Y)&0xFF)) +#define MAX(X,Y) ((X)>=(Y)?(X):(Y)) +#define MIN(X,Y) ((X)>=(Y)?(X):(Y)) + +#define WAIT_N_MS(X) msleep_interruptible(X) + +#define dprintk(args...) \ + do { \ + if (debug) printk(KERN_DEBUG "stb0899: " args); \ + } while (0) + +typedef int BOOL; +typedef char S8; +typedef int S16; +typedef long S32; + +typedef int FE_STB0899_Handle_t; + + + + +#endif + diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/frontends/stb0899_core.c kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/stb0899_core.c --- kernel-2.6.24.4-orig/drivers/media/dvb/frontends/stb0899_core.c 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/stb0899_core.c 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,543 @@ +/* + * stb0899.c + * + * ST DVB-S/DVB-S2 Frontend Driver + * + * Copyright (C) 2001 fnbrd + * & 2002-2004 Andreas Oberritter + * & 2003 Wolfram Joost + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + + + #include + #include + #include + #include + #include + + #include "stb0899.h" + #include "stb0899_common.h" + #include "stb0899_drv.h" + #include "stb0899_chip.h" + +int debug = 1; +module_param(debug, int, 0644); + +//int g_DvbsMode = 0; + +extern FE_STB0899_LOOKUP_t FE_STB0899_CN_LookUp; +extern FE_STB0899_LOOKUP_t FE_STB0899_RF_LookUp; +extern FE_STB0899_LOOKUP_t FE_STB0899_DVBS2RF_LookUp; + + +struct stb0899_state { + struct i2c_adapter *i2c_adap; + const struct stb0899_config *config; + struct dvb_frontend frontend; + u16 g_DvbsMode; + FE_STB0899_Handle_t m_Handle; + u8 signal; + fe_sec_mini_cmd_t minicmd; + fe_sec_tone_mode_t tone; +}; + +int stb0899_set_standard(struct dvb_frontend* fe, u16 *standard) +{ + struct stb0899_state *state = fe->demodulator_priv; + + //printk(KERN_ERR "stb0899_set_standard = %d \n", *standard); + state->g_DvbsMode = *standard; + + return 0; +} + +int STB0899_Lock_Channel (struct stb0899_state * state, u32 freq, u32 symb ) +{ + FE_STB0899_InternalParams_t *pInlParams; + FE_STB0899_SearchParams_t Params; + FE_STB0899_SearchResult_t Results; + FE_STB0899_Error_t ChipError; + FE_STB0899_SignalInfo_t pInfo; + + memset(&Params, 0, sizeof(Params)); + memset(&Results, 0, sizeof(Results)); + memset(&ChipError, 0, sizeof(ChipError)); + memset(&pInfo, 0, sizeof(pInfo)); + + /* Search parameters */ + //printk(KERN_ERR "freq=%ld,symb=%ld\n",freq,symb); + Params.Frequency = freq; /*tuner frequency (in KHz)*/ + Params.SymbolRate = symb; /*symbol rate (in bds)*/ + Params.SearchRange = 40000000; /*range of the search (in Hz)*/ + Params.IQ_Inversion = FE_IQ_AUTO; /* I,Q Inversion */ + + if (state->g_DvbsMode==1) + { + Params.Standard = FE_DVBS2_STANDARD; + Params.Modulation = FE_MOD_8PSK; + } + else if (state->g_DvbsMode==2) + { + Params.Standard = FE_DSS_STANDARD; + Params.Modulation = FE_MOD_QPSK; + } + else + { + Params.Standard = FE_DVBS1_STANDARD; + Params.Modulation = FE_MOD_QPSK; + } + + pInlParams = (FE_STB0899_InternalParams_t *)state->m_Handle; + + /* Launch the search algorithm */ + ChipError = FE_STB0899_Search(state->m_Handle, &Params, &Results); + + if (pInlParams->hTuner->Chip->ChipError || pInlParams->hDemod->ChipError) + { + return -1; + } + else + { + FE_STB0899_GetSignalInfo(state->m_Handle, &pInfo); + + if (pInfo.Locked) + { + printk(KERN_ERR "^_^ Transponder locked\r\n"); + return 0; + } + else + { + printk(KERN_ERR ":( Transponder not found\r\n"); + return -1; + } + } +} + +int st0899_initialize(struct dvb_frontend* fe) +{ + struct stb0899_state *state = fe->demodulator_priv; + + STB0899_InitParams_t DemodInit; /*Demod init params*/ + TUNER_InitParams_t TunerInit; /*Tuner init params*/ + STCHIP_Info_t DemodChip; /*Demod chip init params*/ + STCHIP_Info_t TunerChip; /*Tuner chip init params*/ + STCHIP_Info_t LnbInit; + /* Front-end (Demod + tuner) init params*/ + FE_STB0899_InitParams_t Init; + + u32 STB0899Val[STB0899_NBREGS] = { + 0x30,0x32,0x80,0x4,0x0,0x0,0x0,0x20,0x99,0xa8,0xb,0x11,0xa,0x5,0x0,0x0,0x0,0x0,0xfe, + 0x3,0x7c,0xf4,0xf3,0xfc,0xff,0xff,0x0,0x88,0x5c,0x0,0x0,0x0,0x0,0x33,0x6d,0x90,0x60, //5C <-> F8 + 0x0,0x82,0x82,0x82,0x82,0x82,0x82,0x82,0x82,0x82,0x82,0x82,0x82,0x82,0x82,0x82,0x82, + 0x82,0x82,0x82,0x82,0x82,0xb8,0xba,0x1c,0x82,0x91,0x82,0x7e,0x82,0x82,0x82,0x20,0x82, + 0x82,0x82,0x82,0x82,0x82,0x82,0x82,0x17,0x2,0x0,0x1,0x20,0x0,0xb,0x0,0x0,0x0,0xa,0x2, + 0x3ed097b6,0x3792,0x3fba,0x7aa,0x201,0xf,0x3fb4a20,0x200c17,0x16,0x0,0x0,0x0,0x3ed097b6, + 0x0,0x0,0xf6cdc01,0x0,0x3993,0xd3c6f,0x0,0x0,0x238e38e,0x0,0x0,0x0,0x0,0x0,0x0,0x39488000, + 0x1,0x2,0x0,0x17d3,0x0,0x1,0x7,0x2,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0xffff,0x101,0xfefe,0x404,0xcfcf,0xbebe,0xc2c2,0xc0c0,0xc1c1,0xc1c1,0xc1c1, + 0xc0c1,0xc1c1,0xc0c1,0xc1c1,0xc0c1,0xc1c1,0xc0c1,0xc1c1,0xc1c1,0xc1c1,0xc1c1,0xc1c1,0xc1c1, + 0xc1c1,0xc1c1,0xc1c1,0xc1c1,0xc1c1,0xc1c1,0xc1c1,0xc1c1,0xc1c1,0xc1c1,0xc1c1,0xc1c1,0xc1c1, + 0xc1c1,0xc1c1,0xc1c1,0xc1c1,0xc1c1,0xc1c1,0xc1c1,0xc1c1,0xc1c1,0xc1c1,0xc1c1,0x1,0x5654,0x0,0x20019, + 0x4b3237,0x3dd17,0x8008,0x2a3106,0x6140a,0x8000,0x0,0x0,0x471,0x17b0465,0x2,0x196464,0x603, + 0x2046666,0x10046583,0x10404,0x2aa8a,0x0,0x1,0x500,0x28a0a0,0x0,0x800c17,0xd01,0x0,0x54802, + 0x0,0x0,0x0,0x0,0x0,0x400,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, + 0xffa,0xffd,0xfff,0xffe,0x0,0x36b,0x5,0x1,0x1,0xfff,0xffd,0xfff,0x1,0xfff,0x1,0x1,0x1,0x2,0xffe, + 0xfff,0x0,0xffd,0x0,0xc9,0x1,0x10,0x23,0x4e,0x34,0x84,0xf7,0x87,0x94,0x41,0xf1,0xe3,0xb4,0x10, + 0x30,0xfd,0xff,0xc,0xf,0x6c,0x80,0x6,0x0,0x30,0x7f,0x0,0xbc,0xea,0x31,0x2b,0x80,0x1d,0xa6,0x2f, + 0x68,0x40,0x2f,0x68,0x40,0x2,0xff,0x4,0x5,0x2,0xfd,0x3,0x7,0x8,0xf5,0x0,0x0,0x86,0x2a,0x0,0x0,0x0, + 0x0,0xa,0xad,0x6,0x1,0xb0,0x7a,0x58,0x38,0x34,0x24,0xff,0x19,0xb1,0x42,0x41,0x12,0xc,0x0,0x0,0x69, + 0x0,0x2,0x0,0x0,0x1b,0xb3,0x0,0x0,0xbc,0xcc,0xbd,0x90,0xb6,0x95,0x8d,0x27,0x3,0x5c,0x19,0x48,0x0, + 0x0,0x0,0x77,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0xf0,0x2,0x45,0x60,0xe3,0x0,0x47,0x5,0x18, + 0x19,0x2b,0x0,0x1,0x0,0x26,0x8,0xb4,0x28,0x4b5,0xb4b,0x78,0x1e0,0xa8c0,0xc,0x1,0x545, + 0x40,0x0,0x0,0x8,0x8,0x4db,0x0,0x8,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0xc0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x30 + }; + + u32 DefSTV6100Val[STB6100_NBREGS]= + { + 0x81,0x94,0x4a,0x26,0x3c,0x3b,0xcd,0xdc,0x8f,0x4d,0xeb,0xde + }; + + memset(&DemodInit, 0, sizeof(DemodInit)); + memset(&TunerInit, 0, sizeof(TunerInit)); + memset(&DemodChip, 0, sizeof(DemodChip)); + memset(&TunerChip, 0, sizeof(TunerChip)); + + /* Demodulator */ + DemodInit.Chip = &DemodChip; + DemodInit.NbDefVal = STB0899_NBREGS; + DemodInit.DefVal = STB0899Val; + DemodInit.Chip->RepeaterHost = NULL; + DemodInit.Chip->RepeaterFn = NULL; + DemodInit.Chip->Repeater = FALSE; + DemodInit.Chip->I2cAddr = state->config->demod_address; + DemodInit.Chip->I2c_adap = state->i2c_adap; + strcpy(DemodInit.Chip->Name,"DEMOD"); + + /* Tuner */ + TunerInit.Chip = &TunerChip; + TunerInit.NbDefVal = STB6100_NBREGS; + TunerInit.DefVal = DefSTV6100Val; + TunerInit.Chip->RepeaterFn = STB0899_RepeaterFn; + TunerInit.Chip->Repeater = TRUE; + TunerInit.Chip->I2cAddr = 0xc0 >> 1; + TunerInit.Chip->I2c_adap = state->i2c_adap; + strcpy(TunerInit.Chip->Name,"STB6100"); + + /*Lnbp21*/ + LnbInit.RepeaterHost = NULL; + LnbInit.RepeaterFn = NULL; + LnbInit.Repeater = FALSE; + LnbInit.I2cAddr = 0x10 >> 1; + LnbInit.I2c_adap = state->i2c_adap; + strcpy(LnbInit.Name,"LNBP21"); + + /* Front-end */ + if (state->g_DvbsMode==1) + Init.Standard = FE_DVBS2_STANDARD; + else if (state->g_DvbsMode==2) + Init.Standard = FE_DSS_STANDARD; + else + Init.Standard = FE_DVBS1_STANDARD; + + Init.Clock = FE_PARALLEL_CLOCK; /*Data mode*/ + Init.Parity = FE_PARITY_ON; /*Data parity*/ + Init.STB0899Init = &DemodInit; /*Demod initial params*/ + Init.TunerInit = &TunerInit; /*Tuner initial params*/ + Init.LnbInit = &LnbInit; /*Lnb initial params*/ + + state->m_Handle = FE_STB0899_Init(&Init); + if(state->m_Handle != 0) + { + if ((TunerInit.Chip->ChipError) || (DemodInit.Chip->ChipError)) + { + printk(KERN_ERR "STB0899 initialize finished Dmmodulator Error=%d", DemodInit.Chip->ChipError); + } + else + { + printk(KERN_ERR "STB0899 initialize success \n"); + } + return 0; + } + else + { + printk(KERN_ERR "STB0899 initialize failed"); + return -1; + } +} + + + +int stb0899_set_frontend (struct dvb_frontend* fe, struct dvb_frontend_parameters* params ) +{ + struct stb0899_state *state = fe->demodulator_priv; + + FE_STB0899_InternalParams_t *pInlParams; + int ret = -1; + int Retry = 2; + + while (Retry--) + { + pInlParams = (FE_STB0899_InternalParams_t *)state->m_Handle; + if ( (state->m_Handle == 0) || ( (state->m_Handle != 0) && ((pInlParams->hTuner->Chip->ChipError) || (pInlParams->hDemod->ChipError))) ) + { + st0899_initialize(fe); + + if (state->m_Handle == 0) + { + return -1; //initialize failed + } + } + if(params != NULL) + { + ret = STB0899_Lock_Channel(state, params->frequency, params->u.qpsk.symbol_rate); + } + if (ret == 0) + { + return 0; + } + else + { + if (pInlParams->hTuner->Chip->ChipError || pInlParams->hDemod->ChipError) + { + printk(KERN_ERR "STB0899 search finish,but TunerError=%d,DemodError=%d\n", pInlParams->hTuner->Chip->ChipError, pInlParams->hDemod->ChipError); + } + break; + } + } + return -1; +} + +int stb0899_send_diseqc_msg(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd* cmd) +{ + struct stb0899_state *state = fe->demodulator_priv; + FE_STB0899_InternalParams_t *pInlParams; + + if (state->m_Handle) + { + pInlParams = (FE_STB0899_InternalParams_t *)state->m_Handle; + + ChipSetField(pInlParams->hLnb,FLNBP21_EN,1); + if (FE_STB0899_DiseqcSend(state->m_Handle, cmd->msg, cmd->msg_len)) + return -1; + else + return 0; + } + return 0; +} + +int stb0899_send_diseqc_burst(struct dvb_frontend* fe, fe_sec_mini_cmd_t minicmd) +{ + return 0; +} + +int stb0899_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone) +{ + struct stb0899_state *state = fe->demodulator_priv; + FE_STB0899_InternalParams_t *pInlParams; + + if (state->m_Handle) + { + pInlParams = (FE_STB0899_InternalParams_t *)state->m_Handle; + + if (FE_STB0899_Set22KHZContinues(state->m_Handle, tone)) + { + printk(KERN_ERR "SET_TONE FAIL\n"); + return -1; + } + } + return 0; +} + +int stb0899_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) +{ + struct stb0899_state *state = fe->demodulator_priv; + FE_STB0899_InternalParams_t *pInlParams; + + if (state->m_Handle) + { + pInlParams = (FE_STB0899_InternalParams_t *)state->m_Handle; + switch(voltage) + { + case SEC_VOLTAGE_13: + ChipSetField(pInlParams->hLnb,FLNBP21_EN,1); + ChipSetField(pInlParams->hLnb,FLNBP21_VSEL,0); + break; + + case SEC_VOLTAGE_18: + ChipSetField(pInlParams->hLnb,FLNBP21_EN,1); + ChipSetField(pInlParams->hLnb,FLNBP21_VSEL,1); + break; + + case SEC_VOLTAGE_OFF: + ChipSetField(pInlParams->hLnb,FLNBP21_EN,0); + break; + + default: + return -1; + } + } + return 0; +} + +void stb0899_release(struct dvb_frontend* fe) +{ + struct stb0899_state *state = fe->demodulator_priv; + kfree(state); + +} + +int stb0899_read_status(struct dvb_frontend* fe, fe_status_t* status) +{ + struct stb0899_state *state = fe->demodulator_priv; + FE_STB0899_InternalParams_t *pInlParams; + + *status = 0; + if (state->m_Handle) + { + pInlParams = (FE_STB0899_InternalParams_t *)state->m_Handle; + switch(pInlParams->Standard) + { + case FE_DVBS1_STANDARD: + case FE_DSS_STANDARD: + state->signal = ChipGetField(pInlParams->hDemod, FSTB0899_LOCKEDVIT); + if (state->signal) + *status |= 0x1f; + break; + case FE_DVBS2_STANDARD: + state->signal = (FE_DVBS2_GetState(pInlParams->hDemod, 10) == FE_DVBS2_DATAOK) ? 1 : 0; + if (state->signal) + *status |= 0x1f; + break; + } + } + else + { + return -1; + } + return 0; +} +int stb0899_read_ber(struct dvb_frontend* fe, u32* ber) +{ + struct stb0899_state *state = fe->demodulator_priv; + FE_STB0899_InternalParams_t *pInlParams; + + *ber = 0; + if (state->m_Handle) + { + pInlParams = (FE_STB0899_InternalParams_t *)state->m_Handle; + *ber = FE_STB0899_GetError(pInlParams->hDemod, pInlParams->Standard); + } + else + { + return -1; + } + + return 0; +} +int stb0899_read_signal_strength(struct dvb_frontend* fe, u16* strength) +{ + struct stb0899_state *state = fe->demodulator_priv; + FE_STB0899_InternalParams_t *pInlParams; + + *strength = 0; + if (state->m_Handle) + { + pInlParams = (FE_STB0899_InternalParams_t *)state->m_Handle; + switch(pInlParams->Standard) + { + case FE_DVBS1_STANDARD: + case FE_DSS_STANDARD: + *strength = FE_STB0899_GetRFLevel(pInlParams->hDemod, &FE_STB0899_RF_LookUp, (STB0899_STANDARD)pInlParams->Standard); + break; + case FE_DVBS2_STANDARD: + *strength = FE_STB0899_GetRFLevel(pInlParams->hDemod, &FE_STB0899_DVBS2RF_LookUp, (STB0899_STANDARD)pInlParams->Standard); + break; + } + } + else + { + return -1; + } + + return 0; +} + +int stb0899_read_snr(struct dvb_frontend* fe, u16* snr) +{ + struct stb0899_state *state = fe->demodulator_priv; + FE_STB0899_InternalParams_t *pInlParams; + + *snr = 0; + if (state->m_Handle) + { + pInlParams = (FE_STB0899_InternalParams_t *)state->m_Handle; + + *snr = CarrierGetQuality(pInlParams->hDemod, &FE_STB0899_CN_LookUp, (STB0899_STANDARD)pInlParams->Standard); + } + else + { + return -1; + } + + return 0; +} + +int stb0899_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) +{ + *ucblocks = 0; + return 0; +} + +static int stb0899_i2c_gate_ctrl(struct dvb_frontend* fe, int enable) +{ + struct stb0899_state * state = fe->demodulator_priv; + FE_STB0899_InternalParams_t * pInlParams; + + pInlParams = (FE_STB0899_InternalParams_t *)state->m_Handle; + if (enable) + { + ChipSetOneRegister(pInlParams->hDemod, RSTB0899_I2CRPT, 0x5c|0x80); + } + else + { + ChipSetOneRegister(pInlParams->hDemod, RSTB0899_I2CRPT, 0x5c&0x7f); + } + return 0; +} + + static struct dvb_frontend_ops stb0899_ops = { + .info = { + .name = "ST STB0899 DVB-S2", + .type = FE_QPSK, + .frequency_min = 950000, + .frequency_max = 2150000, + .frequency_stepsize = 125, + .frequency_tolerance = 0, + .symbol_rate_min = 1000000, + .symbol_rate_max = 45000000, + .symbol_rate_tolerance = 500, + .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | + FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | + FE_CAN_FEC_7_8 | FE_CAN_QPSK | + FE_CAN_FEC_AUTO + }, + + .init = st0899_initialize, + .release = stb0899_release, + + .set_standard = stb0899_set_standard, + .set_frontend = stb0899_set_frontend, + + .diseqc_send_master_cmd = stb0899_send_diseqc_msg, + .diseqc_send_burst = stb0899_send_diseqc_burst, + .set_tone = stb0899_set_tone, + .set_voltage = stb0899_set_voltage, + + .i2c_gate_ctrl = stb0899_i2c_gate_ctrl, + + .read_status = stb0899_read_status, + .read_ber = stb0899_read_ber, + .read_signal_strength = stb0899_read_signal_strength, + .read_snr = stb0899_read_snr, + .read_ucblocks = stb0899_read_ucblocks, +}; + +struct dvb_frontend *stb0899_attach(const struct stb0899_config *config, struct i2c_adapter *i2c_adap) +{ + struct stb0899_state *state = NULL; + + state = kmalloc(sizeof (struct stb0899_state), GFP_KERNEL); + if (state == NULL) + goto error; + + state->config = config; + state->i2c_adap = i2c_adap; + state->g_DvbsMode = 1; + memcpy(&state->frontend.ops, &stb0899_ops, sizeof (struct dvb_frontend_ops)); + state->frontend.demodulator_priv = state; + + return &state->frontend; +error: + kfree(state); + return NULL; +} + +MODULE_LICENSE("GPL"); +EXPORT_SYMBOL(stb0899_attach); + diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/frontends/stb0899_drv.c kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/stb0899_drv.c --- kernel-2.6.24.4-orig/drivers/media/dvb/frontends/stb0899_drv.c 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/stb0899_drv.c 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,1451 @@ +/* ------------------------------------------------------------------------- +File Name: STB0899_drv.c + +Description: STB0899 driver LLA V3.4 December/05/2005 + + +author: BJ +---------------------------------------------------------------------------- */ + + +/* includes ---------------------------------------------------------------- */ + +#include +#include "stb0899_drv.h" + + FE_STB0899_LOOKUP_t FE_STB0899_CN_LookUp = { + 20,{ + {15,9600},{20,9450},{30,9000},{40,8250},{50,7970},{60,7360},{70,6770},{80,6200}, + {90,5670},{100, 5190},{110,4740},{120,4360},{130,4010},{140,3710},{150,3440}, + {160,3210},{170,3020},{180,2860},{190,2700},{200,2600} + } +}; + + FE_STB0899_LOOKUP_t FE_STB0899_RF_LookUp = { + 20,{ + {-5,79},{-10,73},{-15,67},{-20,62},{-25,56},{-30,49},{-33,44},{-35,40},{-37,36}, + {-38,33},{-40,27},{-45,4},{-47,-11},{-48,-19},{-50,-29},{-55,-43},{-60,-52}, + {-65,-61},{-67,-65},{-70,-128}, + } +}; + + FE_STB0899_LOOKUP_t FE_STB0899_DVBS2RF_LookUp = { + 15,{ + {-5,2899},{-10, 3330},{-15, 3123},{-20, 3577},{-25, 4004},{-30, 4417},{-35, 4841}, + {-40, 5300},{-45, 5822},{-50, 6491},{-55, 7516},{-60, 9235},{-65, 11374}, + {-70, 12364},{-75, 13063}, + } +}; + +/***************************************************** +**FUNCTION :: FE_STB0899_SetInternalError +**ACTION :: Set the internal error value and location +**PARAMS IN :: Type ==> Type of the error +** Location==> Location of the error +**PARAMS OUT :: pError +**RETURN :: NONE +*****************************************************/ +static void FE_STB0899_SetInternalError(FE_STB0899_ErrorType_t Type,FE_STB0899_Location_t Location,FE_STB0899_InternalError_t *pError) +{ + if(pError != NULL) + { + pError->Type = Type; + pError->Location = Location; + } +} + +/***************************************************** +**FUNCTION :: WaitTuner +**ACTION :: Wait for tuner locked +**PARAMS IN :: TimeOut ->Maximum waiting time (in ms) +**PARAMS OUT:: NONE +**RETURN :: NONE +*****************************************************/ +static void WaitTuner(TUNER_Handle_t hTuner,int TimeOut) +{ + int Time=0; + int TunerLocked = FALSE; + + while(!TunerLocked && (TimeTtiming=>Time to wait for timing loop locked +--PARAMS OUT :: pParams->State =>result of the check +--RETURN :: NOTIMING if timing not locked, TIMINGOK otherwise +--***************************************************/ +static FE_STB0899_SIGNALTYPE_t FE_STB0899_CheckTiming(FE_STB0899_InternalParams_t *pParams) +{ + int locked,timing; + + WAIT_N_MS(pParams->Ttiming); + ChipSetField(pParams->hDemod,FSTB0899_TIMING_LOOP_FREQ,0xf2); + locked=ChipGetField(pParams->hDemod,FSTB0899_TMG_LOCK_IND); + timing=ABS(ChipGetField(pParams->hDemod,FSTB0899_TIMING_LOOP_FREQ)); + if(locked >= 42) + { + if((locked > 48) && (timing >= 110)) + pParams->State = ANALOGCARRIER; + else + pParams->State = TIMINGOK; + } + else + pParams->State = NOTIMING; + + return pParams->State; +} + +/***************************************************** +--FUNCTION :: FE_STB0899_CheckCarrier +--ACTION :: Check for carrier founded +--PARAMS IN :: pParams =>Pointer to FE_STB0899_InternalParams_t structure +--PARAMS OUT :: pParams->State => Result of the check +--RETURN :: NOCARRIER carrier not founded, CARRIEROK otherwise +--***************************************************/ +static FE_STB0899_SIGNALTYPE_t FE_STB0899_CheckCarrier(FE_STB0899_InternalParams_t *pParams) +{ + WAIT_N_MS(pParams->Tderot); /*wait for derotator ok*/ + ChipSetField(pParams->hDemod,FSTB0899_CFD_ON,0); + + if (ChipGetField(pParams->hDemod,FSTB0899_CARRIER_FOUND/*FSTB0899_FDCT*/)) + pParams->State = CARRIEROK; + else + pParams->State = NOCARRIER; + + return pParams->State; +} + +static u32 FE_STB0899_GetErrorCount(STCHIP_Handle_t hChip,ERRORCOUNTER Counter) +{ + u32 lsb=0,msb=0; + + /*Do not modified the read order (lsb first)*/ + switch(Counter) + { + case COUNTER1: + lsb = ChipGetField(hChip,FSTB0899_ERROR_COUNT_LSB); + msb = ChipGetField(hChip,FSTB0899_ERROR_COUNT_MSB); + break; + + case COUNTER2: + lsb = ChipGetField(hChip,FSTB0899_ERROR_COUNT2_LSB); + msb = ChipGetField(hChip,FSTB0899_ERROR_COUNT2_MSB); + break; + + case COUNTER3: + lsb = ChipGetField(hChip,FSTB0899_ERROR_COUNT3_LSB); + msb = ChipGetField(hChip,FSTB0899_ERROR_COUNT3_MSB); + break; + } + + return (MAKEWORD(msb,lsb)); +} + +/***************************************************** +--FUNCTION :: FE_STB0899_CheckData +--ACTION :: Check for data founded +--PARAMS IN :: pParams =>Pointer to FE_STB0899_InternalParams_t structure +--PARAMS OUT :: pParams->State => Result of the check +--RETURN :: NODATA data not founded, DATAOK otherwise +--***************************************************/ +static FE_STB0899_SIGNALTYPE_t FE_STB0899_CheckData(FE_STB0899_InternalParams_t *pParams) +{ + int lock = 0, index=0, dataTime=500; + pParams->State = NODATA; + + /* reset du FEC */ + ChipSetField(pParams->hDemod,FSTB0899_FRESACS,1); + WAIT_N_MS(1); + ChipSetField(pParams->hDemod,FSTB0899_FRESACS,0); + + if(pParams->SymbolRate <= 2000000) + dataTime=2000; + else if(pParams->SymbolRate <= 5000000) + dataTime=1500; + else if(pParams->SymbolRate <= 15000000) + dataTime=1000; + else + dataTime=500; + + /* force search loop */ + ChipSetOneRegister(pParams->hDemod,RSTB0899_DSTATUS2,0x00); + + /* warning : vit locked has to be tested before end_loop */ + while(!(lock = ChipGetField(pParams->hDemod,FSTB0899_LOCKEDVIT)) && + !ChipGetField(pParams->hDemod,FSTB0899_END_LOOPVIT) && indexState = DATAOK; + + return pParams->State; +} + +/***************************************************** +--FUNCTION :: FE_STB0899_TimingTimeConstant +--ACTION :: Compute the amount of time needed by the timing loop to lock +--PARAMS IN :: SymbolRate->symbol rate value +--PARAMS OUT :: NONE +--RETURN :: Timing loop time constant (ms) +--***************************************************/ +static long FE_STB0899_TimingTimeConstant(long SymbolRate) +{ + if(SymbolRate > 0) + return (100000/(SymbolRate/1000)); + else + return 0; +} + +/***************************************************** +--FUNCTION :: FE_STB0899_DerotTimeConstant +--ACTION :: Compute the amount of time needed by the Derotator to lock +--PARAMS IN :: SymbolRate->symbol rate value +--PARAMS OUT :: NONE +--RETURN :: Derotator time constant (ms) +--***************************************************/ +static long FE_STB0899_DerotTimeConstant(long SymbolRate) +{ + if(SymbolRate > 0) + return (100000/(SymbolRate/1000)); + else + return 0; +} + +/**************************************************** +**FUNCTION :: FE_STB0899_GetRollOff +**ACTION :: Read the rolloff value +**PARAMS IN :: hChip==>Handle for the chip +**PARAMS OUT :: NONE +**RETURN :: rolloff +*****************************************************/ +static int FE_STB0899_GetAlpha(STCHIP_Handle_t hChip) +{ + if (ChipGetField(hChip,FSTB0899_MODE_COEF) == 1) + return 20; + else + return 35; +} + +/***************************************************** +**FUNCTION :: BinaryFloatDiv +**ACTION :: float division (with integer) +**PARAMS IN :: NONE +**PARAMS OUT :: NONE +**RETURN :: Derotator frequency (KHz) +*****************************************************/ +static long BinaryFloatDiv(long n1, long n2, int precision) +{ + int i=0; + long result=0; + + /*division de N1 par N2 avec N10*/ + { + if(n1handle to the chip +** MasterClock->Masterclock frequency (Hz) +** SymbolRate->symbol rate (bauds) +**PARAMS OUT :: NONE +**RETURN :: Symbol frequency +*****************************************************/ +static u32 FE_STB0899_SetSymbolRate(STCHIP_Handle_t hChip, u32 MasterClock, u32 SymbolRate) +{ + u32 U32Tmp, U32TmpUp, SymbolRateUp = SymbolRate; + + /* + ** in order to have the maximum precision, the symbol rate entered into + ** the chip is computed as the closest value of the "true value". + ** In this purpose, the symbol rate value is rounded (1 is added on the bit + ** below the LSB ) + */ + + SymbolRateUp += ((SymbolRateUp * 3) / 100); + U32Tmp = BinaryFloatDiv(SymbolRate, MasterClock, 20); + U32TmpUp = BinaryFloatDiv(SymbolRateUp, MasterClock, 20); + + ChipSetFieldImage(hChip, FSTB0899_SYMB_FREQ_UP_HSB, (U32TmpUp >> 12) & 0xFF); + ChipSetFieldImage(hChip, FSTB0899_SYMB_FREQ_UP_MSB, (U32TmpUp >> 4)& 0xFF); + ChipSetFieldImage(hChip, FSTB0899_SYMB_FREQ_UP_LSB, U32TmpUp & 0x0F); + + ChipSetFieldImage(hChip, FSTB0899_SYMB_FREQ_HSB, (U32Tmp >> 12) & 0xFF); + ChipSetFieldImage(hChip, FSTB0899_SYMB_FREQ_MSB, (U32Tmp >> 4) & 0xFF); + ChipSetFieldImage(hChip, FSTB0899_SYMB_FREQ_LSB, U32Tmp & 0x0F); + + + ChipSetRegisters(hChip,RSTB0899_SFRUPH,3); + ChipSetRegisters(hChip,RSTB0899_SFRH,3); + + /*ChipSetOneRegister(hChip,RSTB0899_TMGCFG,0x40);*/ + + return(SymbolRate) ; +} + +/***************************************************** +--FUNCTION :: CarrierWidth +--ACTION :: Compute the width of the carrier +--PARAMS IN :: SymbolRate->Symbol rate of the carrier (Kbauds or Mbauds) +-- RollOff ->Rolloff * 100 +--PARAMS OUT :: NONE +--RETURN :: Width of the carrier (KHz or MHz) +--***************************************************/ +static long CarrierWidth(long SymbolRate, long RollOff) +{ + return (SymbolRate + (SymbolRate * RollOff) / 100); +} + +/***************************************************** +--FUNCTION :: FE_STB0899_InitialCalculations +--ACTION :: Set Params fields that are never changed during search algorithm +--PARAMS IN :: NONE +--PARAMS OUT :: NONE +--RETURN :: NONE +--***************************************************/ +static void FE_STB0899_InitialCalculations(FE_STB0899_InternalParams_t *pParams) +{ + int MasterClock; + + /*Read registers (in burst mode)*/ + ChipGetOneRegister(pParams->hDemod, RSTB0899_AGC1CN); + /*Read AGC1R and AGC2O registers */ + ChipGetRegisters(pParams->hDemod, RSTB0899_AGC1REF, 2); + + /*Initial calculations*/ + MasterClock = FE_STB0899_GetMclkFreq(pParams->hDemod, pParams->Quartz); + pParams->Tagc1 = 0; + pParams->Tagc2 = 0; + pParams->MasterClock = MasterClock; + pParams->Mclk = MasterClock / 65536L; + pParams->RollOff = FE_STB0899_GetAlpha(pParams->hDemod); + + /*DVBS2 Initial calculations */ + /*Set AGC init value to to the midle*/ + pParams->AgcGain = 8154; + ChipSetFieldImage(pParams->hDemod, FSTB0899_IF_GAININIT, pParams->AgcGain); + ChipSetRegisters(pParams->hDemod, RSTB0899_IFAGCCNTRL, 1); + + pParams->RrcAlpha = (FE_DVBS2_RRCAlpha_t)ChipGetField(pParams->hDemod, FSTB0899_RRC_ALPHA); + pParams->AcqMode = CORR_PEAK; + pParams->FreqRange = 4; /*pSearch->FreqRange*/ + pParams->CenterFreq = 0; + pParams->mod = DVBS2_PSK8; + pParams->AveFrameCoarse = 10; + pParams->AveFramefine = 20; + pParams->AgcThreshold = 23; + pParams->AveFrameCoarseAcq = 4; + pParams->AveFramefineAcq = 6; + pParams->AveFrameCoarseTrq = 10; + pParams->AveFramefineTrq = 20; + pParams->AutoReacq = 1; + pParams->TracklockSel = 0; + pParams->Zigzag = 1; + pParams->StepSize = 2; +} + +/***************************************************** +--FUNCTION :: FE_STB0899_SearchTiming +--ACTION :: Perform an Fs/2 zig zag to found timing +--PARAMS IN :: NONE +--PARAMS OUT :: NONE +--RETURN :: NOTIMING if no valid timing had been found, TIMINGOK otherwise +--***************************************************/ +static FE_STB0899_SIGNALTYPE_t FE_STB0899_SearchTiming(FE_STB0899_InternalParams_t *pParams) +{ + short int DerotStep, + DerotFreq = 0, + DerotLimit, + NextLoop = 3; + int index = 0; + + pParams->State = NOTIMING; + + /* timing loop computation & symbol rate optimisation */ + DerotLimit = (short int)((pParams->SubRange / 2L) / pParams->Mclk); + DerotStep = (short int)((pParams->SymbolRate / 2L) / pParams->Mclk); + + while((FE_STB0899_CheckTiming(pParams) != TIMINGOK) && NextLoop) + { + index++; + /*Compute the next derotator position for the zig zag*/ + DerotFreq += index*pParams->Direction * DerotStep; + + if(ABS(DerotFreq) > DerotLimit) + NextLoop--; + + if(NextLoop) + { + ChipSetFieldImage(pParams->hDemod, FSTB0899_CARRIER_FREQUENCY_MSB, MSB(pParams->hTuner->IQ_Wiring * DerotFreq)); + ChipSetFieldImage(pParams->hDemod, FSTB0899_CARRIER_FREQUENCY_LSB, LSB(pParams->hTuner->IQ_Wiring * DerotFreq)); + /*Set the derotator frequency*/ + ChipSetRegisters(pParams->hDemod, RSTB0899_CFRM, 2); + } + /*Change the zigzag direction*/ + pParams->Direction = -pParams->Direction; + } + + if(pParams->State == TIMINGOK) + { + pParams->Results.SymbolRate = pParams->SymbolRate; + /*Get the derotator frequency*/ + ChipGetRegisters(pParams->hDemod, RSTB0899_CFRM, 2); + pParams->DerotFreq = pParams->hTuner->IQ_Wiring * ((short int) MAKEWORD(ChipGetFieldImage(pParams->hDemod, FSTB0899_CARRIER_FREQUENCY_MSB), ChipGetFieldImage(pParams->hDemod, FSTB0899_CARRIER_FREQUENCY_LSB))); + } + + return pParams->State; +} + +/***************************************************** +--FUNCTION :: FE_STB0899_SearchCarrier +--ACTION :: Search a QPSK carrier with the derotator +--PARAMS IN :: +--PARAMS OUT :: NONE +--RETURN :: NOCARRIER if no carrier had been found, CARRIEROK otherwise +--***************************************************/ +static FE_STB0899_SIGNALTYPE_t FE_STB0899_SearchCarrier(FE_STB0899_InternalParams_t *pParams) +{ + short int DerotFreq = 0, + LastDerotFreq = 0, + DerotLimit, + NextLoop = 3; + int index = 0; + + pParams->State = NOCARRIER; + + DerotLimit = (short int)((pParams->SubRange / 2L) / pParams->Mclk); + DerotFreq = pParams->DerotFreq; + + ChipSetField(pParams->hDemod, FSTB0899_CFD_ON, 1); + + do + { + if(FE_STB0899_CheckCarrier(pParams) == NOCARRIER) + { + index++; + LastDerotFreq = DerotFreq; + /*Compute the next derotator position for the zig zag*/ + DerotFreq += index * pParams->Direction * pParams->DerotStep; + + if(ABS(DerotFreq) > DerotLimit) + NextLoop--; + + if(NextLoop) + { + ChipSetField(pParams->hDemod, FSTB0899_CFD_ON, 1); + ChipSetFieldImage(pParams->hDemod, FSTB0899_CARRIER_FREQUENCY_MSB, MSB(pParams->hTuner->IQ_Wiring * DerotFreq)); + ChipSetFieldImage(pParams->hDemod, FSTB0899_CARRIER_FREQUENCY_LSB, LSB(pParams->hTuner->IQ_Wiring * DerotFreq)); + /*Set the derotator frequency*/ + ChipSetRegisters(pParams->hDemod, RSTB0899_CFRM, 2); + } + } + else + { + pParams->Results.SymbolRate = pParams->SymbolRate; + } + /*Change the zigzag direction*/ + pParams->Direction = -pParams->Direction; + } + while((pParams->State != CARRIEROK) && NextLoop); + + if(pParams->State == CARRIEROK) + { + /*Get the derotator frequency*/ + ChipGetRegisters(pParams->hDemod, RSTB0899_CFRM, 2); + pParams->DerotFreq = pParams->hTuner->IQ_Wiring * ((short int) MAKEWORD(ChipGetFieldImage(pParams->hDemod, FSTB0899_CARRIER_FREQUENCY_MSB), ChipGetFieldImage(pParams->hDemod, FSTB0899_CARRIER_FREQUENCY_LSB))); + } + else + { + pParams->DerotFreq = LastDerotFreq; + } + + return pParams->State; +} + +/***************************************************** +--FUNCTION :: FE_STB0899_SearchData +--ACTION :: Search a QPSK carrier with the derotator, even if there is a false lock +--PARAMS IN :: +--PARAMS OUT :: NONE +--RETURN :: NOCARRIER if no carrier had been found, CARRIEROK otherwise +--***************************************************/ +static FE_STB0899_SIGNALTYPE_t FE_STB0899_SearchData(FE_STB0899_InternalParams_t *pParams) +{ + short int DerotFreq, + DerotStep, + DerotLimit, + NextLoop = 3; + int index = 1; + + DerotStep = (short int)((pParams->SymbolRate / 4L) / pParams->Mclk); + DerotLimit = (short int)((pParams->SubRange / 2L) / pParams->Mclk); + DerotFreq = pParams->DerotFreq; + + do + { + if((pParams->State != CARRIEROK) || (FE_STB0899_CheckData(pParams) != DATAOK)) + { + /*Compute the next derotator position for the zig zag*/ + DerotFreq += index * pParams->Direction * DerotStep; + + if(ABS(DerotFreq) > DerotLimit) + NextLoop--; + + if(NextLoop) + { + ChipSetField(pParams->hDemod, FSTB0899_CFD_ON,1); + + ChipSetFieldImage(pParams->hDemod, FSTB0899_CARRIER_FREQUENCY_MSB, MSB(pParams->hTuner->IQ_Wiring * DerotFreq)); + ChipSetFieldImage(pParams->hDemod, FSTB0899_CARRIER_FREQUENCY_LSB, LSB(pParams->hTuner->IQ_Wiring * DerotFreq)); + /*Reset the derotator frequency*/ + ChipSetRegisters(pParams->hDemod, RSTB0899_CFRM, 2); + FE_STB0899_CheckCarrier(pParams); + + index++; + } + } + pParams->Direction = -pParams->Direction;/*Change the zigzag direction*/ + } + while((pParams->State != DATAOK) && NextLoop); + + if(pParams->State == DATAOK) + { + /*Get the derotator frequency*/ + ChipGetRegisters(pParams->hDemod, RSTB0899_CFRM, 2); + pParams->DerotFreq = pParams->hTuner->IQ_Wiring * ((short int) MAKEWORD(ChipGetFieldImage(pParams->hDemod, FSTB0899_CARRIER_FREQUENCY_MSB), ChipGetFieldImage(pParams->hDemod, FSTB0899_CARRIER_FREQUENCY_LSB))); + } + + return pParams->State; +} + +/**************************************************** +--FUNCTION :: FE_STB0899_CheckRange +--ACTION :: Check if the founded frequency is in the correct range +--PARAMS IN :: pParams->BaseFreq => +--PARAMS OUT :: pParams->State =>Result of the check +--RETURN :: RANGEOK if check success, OUTOFRANGE otherwise +--***************************************************/ +static FE_STB0899_SIGNALTYPE_t FE_STB0899_CheckRange(FE_STB0899_InternalParams_t *pParams) +{ + int RangeOffset, + TransponderFrequency; + + RangeOffset = pParams->SearchRange/2000; + TransponderFrequency = pParams->Frequency + (pParams->DerotFreq * pParams->Mclk) / 1000; + + if((TransponderFrequency >= pParams->BaseFreq - RangeOffset) + && (TransponderFrequency <= pParams->BaseFreq + RangeOffset)) + pParams->State = RANGEOK; + else + pParams->State = OUTOFRANGE; + + return pParams->State; +} + +/**************************************************** +--FUNCTION :: FirstSubRange +--ACTION :: Compute the first SubRange of the search +--PARAMS IN :: pParams->SearchRange +--PARAMS OUT :: pParams->SubRange +--RETURN :: NONE +--***************************************************/ +static void FirstSubRange(FE_STB0899_InternalParams_t *pParams) +{ + int maxsubrange; + + maxsubrange = TunerGetBandwidth(pParams->hTuner) - CarrierWidth(pParams->SymbolRate, pParams->RollOff) / 2; + + if(maxsubrange > 0) + pParams->SubRange = MIN(pParams->SearchRange, maxsubrange); + else + pParams->SubRange = 0; + pParams->Frequency = pParams->BaseFreq; + pParams->TunerOffset = 0L; + + pParams->SubDir = 1; +} +/**************************************************** +--FUNCTION :: NextSubRange +--ACTION :: Compute the next SubRange of the search +--PARAMS IN :: Frequency->Start frequency +-- pParams->SearchRange +--PARAMS OUT :: pParams->SubRange +--RETURN :: NONE +--***************************************************/ +static void NextSubRange(FE_STB0899_InternalParams_t *pParams) +{ + long OldSubRange; + + if(pParams->SubDir > 0) + { + OldSubRange = pParams->SubRange; + pParams->SubRange = MIN((pParams->SearchRange/2) - (pParams->TunerOffset + pParams->SubRange/2), pParams->SubRange); + if(pParams->SubRange < 0) + pParams->SubRange = 0; + pParams->TunerOffset += (OldSubRange + pParams->SubRange) / 2; + } + + pParams->Frequency = pParams->BaseFreq + (pParams->SubDir * pParams->TunerOffset) / 1000; + pParams->SubDir = -pParams->SubDir; +} + +/***************************************************** +--FUNCTION :: FE_STB0899_Algo +--ACTION :: Search for Signal, Timing, Carrier and then data at a given Frequency, +-- in a given range +--PARAMS IN :: NONE +--PARAMS OUT :: NONE +--RETURN :: Type of the founded signal (if any) +--***************************************************/ +FE_STB0899_SIGNALTYPE_t FE_STB0899_Algo(FE_STB0899_InternalParams_t *pParams) +{ + pParams->Frequency = pParams->BaseFreq; + pParams->Direction = 1; + + FE_STB0899_SetSymbolRate(pParams->hDemod, pParams->MasterClock, pParams->SymbolRate); + + /* Carrier loop optimization versus symbol rate */ + if(pParams->SymbolRate <= 5000000) + ChipSetField(pParams->hDemod, FSTB0899_ALPHA, 9); + else + ChipSetField(pParams->hDemod, FSTB0899_ALPHA, 7); + + if(pParams->SymbolRate <= 2000000) + ChipSetField(pParams->hDemod, FSTB0899_BETA, 0x17); + else if(pParams->SymbolRate <= 5000000) + ChipSetField(pParams->hDemod, FSTB0899_BETA, 0x1C); + else if(pParams->SymbolRate <= 15000000) + ChipSetField(pParams->hDemod, FSTB0899_BETA, 0x22); + else if(pParams->SymbolRate <= 30000000) + ChipSetField(pParams->hDemod, FSTB0899_BETA, 0x27); + else + ChipSetField(pParams->hDemod, FSTB0899_BETA, 0x29); + + /*Initial calculations*/ + /*step of DerotStep/1000 * Fsymbol*/ + pParams->DerotStep = pParams->DerotPercent*((S16)((pParams->SymbolRate/1000L)/pParams->Mclk)); + pParams->Ttiming = (S16)(FE_STB0899_TimingTimeConstant(pParams->SymbolRate)); + pParams->Tderot = (S16)(FE_STB0899_DerotTimeConstant(pParams->SymbolRate)); + pParams->Tdata = 500; + + ChipSetField(pParams->hDemod,FSTB0899_FRESRS, 1); /*Reset Stream merger*/ + + FirstSubRange(pParams); + + /*Initialisations*/ + ChipSetFieldImage(pParams->hDemod, FSTB0899_CARRIER_FREQUENCY_MSB, 0); + ChipSetFieldImage(pParams->hDemod, FSTB0899_CARRIER_FREQUENCY_LSB, 0); + /*Reset of the derotator frequency*/ + ChipSetRegisters(pParams->hDemod, RSTB0899_CFRM, 2); + ChipSetField(pParams->hDemod, FSTB0899_TIMING_LOOP_FREQ, 0xf2); + ChipSetField(pParams->hDemod, FSTB0899_CFD_ON,1); + + pParams->DerotFreq = 0; + pParams->State = NOAGC1; + + /*Move the tuner*/ + TunerSetFrequency(pParams->hTuner, pParams->Frequency); + pParams->Frequency = TunerGetFrequency(pParams->hTuner); + + if (pParams->hTuner->Chip->ChipError) + { + return NOCARRIER; + } + + /*Temporisations*/ + /*Wait for agc1,agc2 and timing loop*/ + WAIT_N_MS(pParams->Tagc1 + pParams->Tagc2 + pParams->Ttiming); + /*Is tuner Locked? (wait 100 ms maxi)*/ + WaitTuner(pParams->hTuner, 100); + + pParams->State = AGC1OK; /* No AGC test actually */ + + /*There is signal in the band*/ + if(pParams->SymbolRate <= (S32)(TunerGetBandwidth(pParams->hTuner)/2)) + FE_STB0899_SearchTiming(pParams); /*For low rates (SCPC)*/ + else + FE_STB0899_CheckTiming(pParams); /*For high rates (MCPC)*/ + + if(pParams->State == TIMINGOK) + { //printk(KERN_ERR "TIMINGOK\n"); + if(FE_STB0899_SearchCarrier(pParams) == CARRIEROK) + { //printk(KERN_ERR "CARRIEROK\n"); + /*Check for data*/ + if(FE_STB0899_SearchData(pParams) == DATAOK) + { //printk(KERN_ERR "DATAOK\n"); + if(FE_STB0899_CheckRange(pParams) == RANGEOK) + { //printk(KERN_ERR "RANGEOK\n"); + pParams->Results.Frequency = pParams->Frequency + (pParams->DerotFreq * (pParams->Mclk) / 1000); + pParams->Results.PunctureRate = (FE_STB0899_Rate_t)ChipGetField(pParams->hDemod, FSTB0899_VIT_CURPUN); + } + } + } + } + if(pParams->State != RANGEOK) + NextSubRange(pParams); + + ChipSetField(pParams->hDemod, FSTB0899_FRESRS, 0); /*release Stream merger reset*/ + ChipSetField(pParams->hDemod, FSTB0899_CFD_ON, 0); /*Disable Carrier detector*/ + + ChipGetRegisters(pParams->hDemod, RSTB0899_EQUAI1, 10); + + pParams->Results.SignalType = pParams->State; + + /*if locked and range is ok set Kdiv value*/ + if(pParams->State == RANGEOK) + { + switch(pParams->Results.PunctureRate) + { + case 13: /*1/2*/ + ChipSetField(pParams->hDemod, FSTB0899_KDIVIDER, 0x1a/*36*/); + break; + + case 18: /*2/3*/ + ChipSetField(pParams->hDemod, FSTB0899_KDIVIDER, 44/*0x27*/); + break; + + case 21: /*3/4*/ + ChipSetField(pParams->hDemod, FSTB0899_KDIVIDER,/*0x34*/60); + break; + + case 24: /*5/6*/ + ChipSetField(pParams->hDemod, FSTB0899_KDIVIDER,75/*0x4f*/); + break; + + case 25: /*6/7*/ + ChipSetField(pParams->hDemod, FSTB0899_KDIVIDER,/*0x5c*/80); + break; + + case 26: /*7/8*/ + ChipSetField(pParams->hDemod, FSTB0899_KDIVIDER,94/*0x6a*/); + break; + } + } + return pParams->State; +} + +FE_DVBS2_State FE_STB0899_DVBS2Algo(FE_STB0899_InternalParams_t *pParams) +{ + FE_STB0899_DVBS2_InitParams_t initParams; + FE_DVBS2_ReacquireParams_t racqParams; + FE_DVBS2_ModCod_t modCode; + + S32 offsetfreq,searchTime,pilots; + + /*Init Params Initialization*/ + initParams.RRCAlpha = pParams->RrcAlpha; + initParams.ModeMode = pParams->mod; + initParams.SymbolRate = pParams->DVBS2SymbolRate; + initParams.MasterClock = pParams->MasterClock; + initParams.CarrierFrequency = 0; + initParams.AveFrameCoarse = pParams->AveFrameCoarse; + initParams.AveFramefine = pParams->AveFramefine; + initParams.AgcThreshold = pParams->AgcThreshold; + + /*Reacquire Params initialization*/ + racqParams.AcqMode = pParams->AcqMode; + racqParams.SymbolRate = pParams->DVBS2SymbolRate; + racqParams.MasterClock = pParams->MasterClock; + racqParams.FreqRange = pParams->SearchRange / 1000000/*pParams->FreqRange*/; + racqParams.CenterFreq = pParams->CenterFreq; + racqParams.AveFrameCoarseAcq = pParams->AveFrameCoarseAcq; + racqParams.AveFramefineAcq = pParams->AveFramefineAcq; + racqParams.AveFrameCoarseTrq = pParams->AveFrameCoarseTrq; + racqParams.AveFramefineTrq = pParams->AveFramefineTrq; + racqParams.AutoReacq = pParams->AutoReacq; + racqParams.TracklockSel = pParams->TracklockSel; + racqParams.Zigzag = pParams->Zigzag; + racqParams.StepSize = pParams->StepSize; + + if(pParams->DVBS2SymbolRate <= 2000000) + searchTime = 5000; + else if(pParams->DVBS2SymbolRate <= 5000000) + searchTime = 2500; + else if(pParams->DVBS2SymbolRate <= 10000000) + searchTime = 1500; + else if (pParams->DVBS2SymbolRate <= 15000000) + searchTime = 700; + else if (pParams->DVBS2SymbolRate <= 20000000) + searchTime = 500; + else if (pParams->DVBS2SymbolRate <= 25000000) + searchTime = 200; + else + searchTime = 150; + + /*move tuner*/ + TunerSetFrequency(pParams->hTuner, pParams->Frequency); + pParams->Frequency = TunerGetFrequency(pParams->hTuner); + /*Temporisations*/ + WaitTuner(pParams->hTuner, 100); /*Is tuner Locked?(wait 100 ms maxi)*/ + + /*Set IF AGC to Acquire value*/ + ChipSetFieldImage(pParams->hDemod, FSTB0899_IF_LOOPGAIN, 4); + ChipSetRegisters(pParams->hDemod, RSTB0899_IFAGCCNTRL, 1); + + ChipSetFieldImage(pParams->hDemod, FSTB0899_IF_AGC_DUMPPER, 0); + ChipSetRegisters(pParams->hDemod, RSTB0899_IFAGCCNTRL2, 1); + + /*Initialisations*/ + FE_DVBS2_InitialCalculations(pParams->hDemod, &initParams); + + /*IQ swap setting*/ + if((pParams->SpectralInv == FE_IQ_AUTO) || (pParams->SpectralInv == FE_IQ_NORMAL)) + { + /* I,Q Spectrum Set to Normal*/ + ChipSetFieldImage(pParams->hDemod, FSTB0899_SPECTRUM_INVERT, 0); + ChipSetRegisters(pParams->hDemod, RSTB0899_DMDCNTRL2, 1); + } + else + { + /* I,Q Spectrum Inverted*/ + ChipSetFieldImage(pParams->hDemod, FSTB0899_SPECTRUM_INVERT, 1); + ChipSetRegisters(pParams->hDemod, RSTB0899_DMDCNTRL2, 1); + } + + FE_DVBS2_Reacquire(pParams->hDemod, &racqParams); + /*Wait for UWP,CSM and DATA LOCK searchTime ms max*/ + pParams->Results.DVBS2SignalType = pParams->DVBS2State = FE_DVBS2_GetState(pParams->hDemod, searchTime); + + if(pParams->DVBS2State != FE_DVBS2_DATAOK) + { + if(pParams->SpectralInv == FE_IQ_AUTO) + { + /* I,Q Spectrum Invertion*/ + ChipSetFieldImage(pParams->hDemod, FSTB0899_SPECTRUM_INVERT, 1); + ChipSetRegisters(pParams->hDemod, RSTB0899_DMDCNTRL2, 1); + /* start acquistion process */ + FE_DVBS2_Reacquire(pParams->hDemod, &racqParams); + /*Whait for UWP,CSM and data LOCK 200ms max*/ + pParams->Results.DVBS2SignalType = pParams->DVBS2State = FE_DVBS2_GetState(pParams->hDemod, searchTime); + if(pParams->DVBS2State == FE_DVBS2_DATAOK) + pParams->SpectralInv = FE_IQ_SWAPPED; + } + } + /*Set IF AGC to tracking value*/ + ChipSetFieldImage(pParams->hDemod, FSTB0899_IF_LOOPGAIN, 3); + ChipSetRegisters(pParams->hDemod, RSTB0899_IFAGCCNTRL, 1); + + ChipSetFieldImage(pParams->hDemod, FSTB0899_IF_AGC_DUMPPER, 7); + ChipSetRegisters(pParams->hDemod, RSTB0899_IFAGCCNTRL2, 1); + + if(pParams->DVBS2State == FE_DVBS2_DATAOK) + { + modCode = (FE_DVBS2_ModCod_t)FE_DVBS2_GetModCod(pParams->hDemod); + pilots=ChipGetFieldImage(pParams->hDemod, FSTB0899_UWP_DECODED_MODCODE) & 0x01; + + if((((10*pParams->MasterClock) / (pParams->DVBS2SymbolRate/10)) <= 400) && (INRANGE(FE_QPSK_12, modCode, FE_QPSK_910)) && (pilots == 1)) + { + FE_DVBS2_CSMInitialize(pParams->hDemod, pilots, modCode, pParams->DVBS2SymbolRate, pParams->MasterClock); + /*Wait for UWP,CSM and data LOCK 20ms max*/ + pParams->Results.DVBS2SignalType = pParams->DVBS2State = FE_DVBS2_GetState(pParams->hDemod, 20); + } + + /*if locked store signal parameters*/ + offsetfreq = ChipGetField(pParams->hDemod, FSTB0899_CRL_FREQUENCY); + offsetfreq = offsetfreq / (PowOf2(30) / 1000); + offsetfreq *= (pParams->MasterClock / 1000000); + if(ChipGetFieldImage(pParams->hDemod, FSTB0899_SPECTRUM_INVERT)) + offsetfreq *= -1; + + pParams->Results.Frequency = TunerGetFrequency(pParams->hTuner) - offsetfreq; + pParams->Results.DVBS2SymbolRate = FE_DVBS2_GetSymbolRate(pParams->hDemod, pParams->MasterClock); + pParams->Results.ModCode = (FE_DVBS2_ModCod_t)FE_DVBS2_GetModCod(pParams->hDemod); + pParams->Results.Pilots = (BOOL)ChipGetFieldImage(pParams->hDemod, FSTB0899_UWP_DECODED_MODCODE) & 0x01; + pParams->Results.FrameLength = (FE_DVBS2_FRAME)((ChipGetFieldImage(pParams->hDemod, FSTB0899_UWP_DECODED_MODCODE) >> 1) & 0x01); + + /*Set AGC init value to to the founded AGC level*/ + pParams->AgcGain = ChipGetField(pParams->hDemod, FSTB0899_IF_AGCGAIN); + ChipSetFieldImage(pParams->hDemod, FSTB0899_IF_GAININIT, pParams->AgcGain); + ChipSetRegisters(pParams->hDemod, RSTB0899_IFAGCCNTRL, 1); + + /*if QPSK 1/2 ,QPSK 3/5 or QPSK 2/3 set IF AGC reference to 16 otherwise 32*/ + if(pParams->Results.ModCode <= FE_QPSK_23) + { + ChipSetFieldImage(pParams->hDemod, FSTB0899_IF_AGCREF, 16); + ChipSetRegisters(pParams->hDemod, RSTB0899_IFAGCCNTRL, 1); + } + else + { + ChipSetFieldImage(pParams->hDemod,FSTB0899_IF_AGCREF,32); + ChipSetRegisters(pParams->hDemod,RSTB0899_IFAGCCNTRL,1); + } + } + return pParams->DVBS2State; +} + +/*Symbol Rate in Hz,Mclk in Hz */ +static void FE_STB0899_SetIterScal(STCHIP_Handle_t hChip, u32 MasterClock, u32 SymbolRate) +{ + S32 iTerScal; + + iTerScal = 17 * (MasterClock / 1000); + iTerScal += 410000; + iTerScal /= (SymbolRate / 1000000); + iTerScal /= 1000; + + if(iTerScal > 150) + iTerScal = 150; + + ChipSetField(hChip, FSTB0899_ITERATION_SCALE, iTerScal); +} + +/***************************************************** +--FUNCTION :: FE_STB0899_Init +--ACTION :: Initialisation of the STB0899 chip +--PARAMS IN :: pInit==>pointer to stb0899_state structure +--PARAMS OUT :: NONE +--RETURN :: Handle to STB0899 +--***************************************************/ +FE_STB0899_Handle_t FE_STB0899_Init(FE_STB0899_InitParams_t *pInit) +{ + FE_STB0899_InternalParams_t *pParams = NULL; + + /* Internal params structure allocation */ + pParams = (FE_STB0899_InternalParams_t *)kmalloc(sizeof(FE_STB0899_InternalParams_t), GFP_KERNEL); + + if(pParams != NULL) + { + /* Chip initialisation */ + pParams->hDemod = STB0899_Init(pInit->STB0899Init); + + if(pInit->TunerInit->Chip->Repeater) + pInit->TunerInit->Chip->RepeaterHost = pParams->hDemod; + pParams->hTuner = STTunerInit(pInit->TunerInit); + pParams->hLnb = LNBP21_Init(pInit->LnbInit); + + if((pParams->hDemod != NULL) && (!pParams->hDemod->ChipError)) + { + FE_STB0899_SetStandard(pParams->hDemod, (STB0899_STANDARD)pInit->Standard); + + pParams->Quartz = 27000000; + + switch(pInit->Clock) + { + case FE_PARALLEL_CLOCK: + /*TS_CLK = MCLK , if parallel TS disable output fifo */ + ChipSetField(pParams->hDemod, FSTB0899_OUTRS_PS, 0x00); + ChipSetOneRegister(pParams->hDemod, RSTB0899_TSOUT, 0x7f); + break; + + case FE_SERIAL_MASTER_CLOCK: + /*TS_CLK = MCLK if serial TS do not disable output fifo , set TS_clk ratio to 1 */ + ChipSetField(pParams->hDemod, FSTB0899_OUTRS_PS, 0x01); + ChipSetOneRegister(pParams->hDemod, RSTB0899_TSOUT, 0x23); + break; + + default: + break; + } + + switch(pInit->Parity) + { + case FE_PARITY_ON: + ChipSetField(pParams->hDemod, FSTB0899_CLK_POL, 0x00); + break; + + case FE_PARITY_OFF: + ChipSetField(pParams->hDemod, FSTB0899_CLK_POL, 0x01); + break; + + default: + break; + } + FE_STB0899_InitialCalculations(pParams); + } + else + { + kfree(pParams); + pParams = NULL; + } + } + return (FE_STB0899_Handle_t) pParams; +} + +/***************************************************** +--FUNCTION :: FE_STB0899_SetMclk +--ACTION :: Set demod Master Clock +--PARAMS IN :: Handle==>Front End Handle + :: Mclk : demod master clock + :: ExtClk external Quartz +--PARAMS OUT :: NONE. +--RETURN :: Error (if any) +--***************************************************/ +FE_STB0899_Error_t FE_STB0899_SetMclk(FE_STB0899_Handle_t Handle, u32 Mclk, u32 ExtClk) +{ + FE_STB0899_Error_t st_error = FE_NO_ERROR; + FE_STB0899_InternalParams_t * pParams = (FE_STB0899_InternalParams_t *)Handle; + + u32 mDiv; + if(pParams == NULL) + st_error = FE_INVALID_HANDLE; + else + { + mDiv = ((6 * Mclk) / ExtClk) - 1; + ChipSetField(pParams->hDemod, FSTB0899_MDIV, mDiv); + pParams->MasterClock = FE_STB0899_GetMclkFreq(pParams->hDemod, pParams->Quartz); + } + return(FE_NO_ERROR); +} + +FE_STB0899_Error_t FE_STB0899_Search(FE_STB0899_Handle_t Handle, FE_STB0899_SearchParams_t *pSearch, FE_STB0899_SearchResult_t *pResult) +{ + FE_STB0899_Error_t st_error = FE_NO_ERROR; + FE_STB0899_InternalParams_t *pParams; + + if(Handle != 0) + { + pParams = (FE_STB0899_InternalParams_t *) Handle; + FE_STB0899_SetInternalError(FE_IERR_NO, FE_LOC_NOWHERE, &pParams->Inl_Error); + pParams->Standard = pSearch->Standard; + if((INRANGE(1000000, pSearch->SymbolRate, 45000000)) && (INRANGE(1000000, pSearch->SearchRange, 50000000))) + { + printk(KERN_ERR "inrange 1-45M\n"); + FE_STB0899_SetStandard(pParams->hDemod, (STB0899_STANDARD)pSearch->Standard); + + /*Set tuner Gain */ + if(pSearch->SymbolRate > 15000000) + TunerSetGain(pParams->hTuner, 8); + else if(pSearch->SymbolRate > 5000000) + TunerSetGain(pParams->hTuner,12); + else + TunerSetGain(pParams->hTuner,14); + + /*For Low Symbol Rate (<=5Mbs) set Mclk to 45MHz, else use 108MHz*/ + if(pSearch->SymbolRate <= 5000000) + { + FE_STB0899_SetMclk(Handle, 45000000, pParams->Quartz); + } + else + { //printk(KERN_ERR "pSearch->SymbolRate > 5M\n"); + FE_STB0899_SetMclk(Handle, 108000000, pParams->Quartz); + } + + switch(pSearch->Standard) + { + case FE_DVBS1_STANDARD: + case FE_DSS_STANDARD: + printk(KERN_ERR "FE_DVBS1_STANDARD\n"); + /* Fill pParams structure with search parameters */ + pParams->BaseFreq = pSearch->Frequency; + pParams->SymbolRate = pSearch->SymbolRate; + pParams->SearchRange = pSearch->SearchRange; + pParams->DerotPercent = 10; + TunerSetBandwidth(pParams->hTuner, (13 * (CarrierWidth(pParams->SymbolRate, pParams->RollOff) + 10000000)) / 10); + pParams->TunerBW = TunerGetBandwidth(pParams->hTuner); + /*Set DVB-S1 AGC*/ + ChipSetOneRegister(pParams->hDemod, RSTB0899_AGCRFCFG, 0x11); + /* Run the search algorithm */ + if((FE_STB0899_Algo(pParams) == RANGEOK) && (pParams->hDemod->ChipError == CHIPERR_NO_ERROR)) + { + pResult->Locked = TRUE; + /* update results */ + pResult->Frequency =pParams->Results.Frequency; + pResult->SymbolRate = pParams->Results.SymbolRate; + pResult->Rate = pParams->Results.PunctureRate; + } + else + { + pResult->Locked = FALSE; + + switch(pParams->Inl_Error.Type) + { + case FE_IERR_I2C: + st_error = FE_I2C_ERROR; + break; + + case FE_IERR_NO: + default: + st_error = FE_SEARCH_FAILED; + break; + } + } + break; + + case FE_DVBS2_STANDARD: + printk(KERN_ERR "FE_DVBS2_STANDARD\n"); + /* Fill pParams structure with search parameters */ + pParams->Frequency = pSearch->Frequency; + pParams->BaseFreq = pSearch->Frequency; + pParams->DVBS2SymbolRate = pSearch->SymbolRate; + pParams->SpectralInv = pSearch->IQ_Inversion; + + pParams->SearchRange = pSearch->SearchRange; + TunerSetBandwidth(pParams->hTuner, (13 * (FE_DVBS2_CarrierWidth(pParams->DVBS2SymbolRate,pParams->RrcAlpha) + 10000000)) / 10); + pParams->TunerBW = TunerGetBandwidth(pParams->hTuner); + + /*Set DVB-S2 AGC*/ + ChipSetOneRegister(pParams->hDemod, RSTB0899_AGCRFCFG, 0x1c); + + /*Set IterScale =f(MCLK,SYMB,MODULATION*/ + FE_STB0899_SetIterScal(pParams->hDemod, pParams->MasterClock, pParams->DVBS2SymbolRate); + + /* Run the DVBS2 search algorithm */ + if((FE_STB0899_DVBS2Algo(pParams) == FE_DVBS2_DATAOK) && (pParams->hDemod->ChipError == CHIPERR_NO_ERROR)) + { + pResult->Locked = TRUE; + /* update results */ + pResult->Frequency =pParams->Results.Frequency; + pResult->SymbolRate = pParams->Results.DVBS2SymbolRate; + pResult->ModCode = pParams->Results.ModCode; + pResult->Pilots = pParams->Results.Pilots; + pResult->FrameLength = pParams->Results.FrameLength; + } + else + { + pResult->Locked = FALSE; + + switch(pParams->Inl_Error.Type) + { + case FE_IERR_I2C: + st_error = FE_I2C_ERROR; + break; + + case FE_IERR_NO: + default: + st_error = FE_SEARCH_FAILED; + break; + } + } + break; + + default: + st_error = FE_BAD_PARAMETER; + break; + } + } + else + st_error = FE_BAD_PARAMETER; + } + else + st_error=FE_INVALID_HANDLE; + + return st_error; +} + +/***************************************************** +--FUNCTION :: FE_STB0899_GetRFLevel +--ACTION :: Return power of the signal +--PARAMS IN :: NONE +--PARAMS OUT :: NONE +--RETURN :: Power of the signal (dBm), 0 if no signal +--***************************************************/ +u16 FE_STB0899_GetRFLevel(STCHIP_Handle_t hChip,FE_STB0899_LOOKUP_t *lookup,STB0899_STANDARD Standard) +{ + u8 Imin, Imax, i; + S16 agcGain = 0,rfLevel = 0; + + if((lookup != NULL) && lookup->size) + { + switch(Standard) + { + case FE_DVBS1_STANDARD: + case FE_DSS_STANDARD: + agcGain = ChipGetField(hChip,FSTB0899_AGCIQ_VALUE); + break; + + case FE_DVBS2_STANDARD: + agcGain = ChipGetField(hChip,FSTB0899_IF_AGCGAIN); + break; + } + Imin = 0; + Imax = lookup->size-1; + + if(INRANGE(lookup->table[Imin].regval,agcGain,lookup->table[Imax].regval)) + { + while((Imax-Imin)>1) + { + i=(Imax+Imin)/2; + + if(INRANGE(lookup->table[Imin].regval,agcGain,lookup->table[i].regval)) + Imax = i; + else + Imin = i; + } + rfLevel =(((S32)agcGain - lookup->table[Imin].regval) * (lookup->table[Imax].realval - lookup->table[Imin].realval) / (lookup->table[Imax].regval - lookup->table[Imin].regval)) + lookup->table[Imin].realval + 100; + } + else + rfLevel = -100+100; + } + return (u16)rfLevel; +} + +/***************************************************** +--FUNCTION :: CarrierGetQuality +--ACTION :: Return the carrier to noise of the current carrier +--PARAMS IN :: NONE +--PARAMS OUT :: NONE +--RETURN :: C/N of the carrier, 0 if no carrier +--***************************************************/ +u16 CarrierGetQuality(STCHIP_Handle_t hChip, FE_STB0899_LOOKUP_t *lookup, STB0899_STANDARD Standard) +{ + u16 regval, Imin, Imax, i; + u16 c_n = 0, quant, val2; + + switch(Standard) + { + case FE_DVBS1_STANDARD: + case FE_DSS_STANDARD: + if(ChipGetField(hChip,FSTB0899_CARRIER_FOUND)) + { + if((lookup != NULL) && lookup->size) + { + ChipGetRegisters(hChip, RSTB0899_NIRM, 2); + ChipGetRegisters(hChip, RSTB0899_NIRL, 2); + + regval = MAKEWORD(ChipGetFieldImage(hChip, FSTB0899_NOISE_IND_MSB), ChipGetFieldImage(hChip, FSTB0899_NOISE_IND_LSB)); + + Imin = 0; + Imax = lookup->size-1; + + if(INRANGE(lookup->table[Imin].regval, regval, lookup->table[Imax].regval)) + { + while((Imax-Imin) > 1) + { + i = (Imax + Imin) / 2; + if(INRANGE(lookup->table[Imin].regval, regval, lookup->table[i].regval)) + Imax = i; + else + Imin = i; + } + c_n = ((regval - lookup->table[Imin].regval) * (lookup->table[Imax].realval - lookup->table[Imin].realval) / (lookup->table[Imax].regval - lookup->table[Imin].regval)) + lookup->table[Imin].realval; + + c_n = (int)(c_n / 2); + if (c_n >= 100) + c_n = 98; + } + else if(regval < lookup->table[Imin].regval) + c_n = 98; + } + } + + break; + + case FE_DVBS2_STANDARD: + + quant = ChipGetField(hChip, FSTB0899_UWP_ESN0_QUANT); + c_n = FE_DVBS2_GetUWPEsNo(hChip, quant); + if(c_n == 1) + c_n = 301; /*C/N = 30.1*/ + else if(c_n == 2) + c_n = 270; /*C/N = 27*/ + else + { + val2 = (long)(-10 * (Log10Int((long)(c_n)) - 2 * Log10Int((long)(quant)))); + val2 = MULT32X32(val2, 646456993L); + val2 *= 10; + c_n = (u16)(((unsigned long)(val2)) / PowOf2(24)); + } + break; + } + + return c_n; +} + +u32 FE_STB0899_GetError(STCHIP_Handle_t hChip, u32 Standrad) +{ + u32 ber = 0,i; + + switch(Standrad) + { + case FE_DVBS1_STANDARD: + case FE_DSS_STANDARD: + /* force to viterbi bit error */ + ChipSetOneRegister(hChip, RSTB0899_ERRCTRL1, 0x3D); + ChipGetOneRegister(hChip, RSTB0899_VSTATUS); + + /* Average 5 ber values */ + WAIT_N_MS(1000); + for(i=0; i<5; i++) + { + WAIT_N_MS(100); + ber += FE_STB0899_GetErrorCount(hChip, COUNTER1); + } + + ber /= 5; + /*Check for carrier*/ + if(ChipGetFieldImage(hChip, FSTB0899_PRFVIT)) + { + /*Error Rate*/ + ber *= 9766; + /*theses two lines => ber = ber * 10^7*/ + ber /= (-1 + PowOf2(0 + 2*ChipGetFieldImage(hChip, FSTB0899_NOE))); + ber /= 8; + } + break; + + case FE_DVBS2_STANDARD: + /*force to DVBS2 PER*/ + ChipSetOneRegister(hChip, RSTB0899_ERRCTRL1, 0xB6); + ChipGetOneRegister(hChip, RSTB0899_VSTATUS); + + /*Average 5 ber values*/ + for(i=0; i<5; i++) + { + WAIT_N_MS(100); + ber += FE_STB0899_GetErrorCount(hChip, COUNTER1); + } + + ber *= 10000000; + ber /= (-1 + PowOf2(4 + 2 * ChipGetFieldImage(hChip, FSTB0899_NOE))); + break; + } + return ber; +} + +/***************************************************** +--FUNCTION :: FE_STB0899_GetSignalInfo +--ACTION :: Return informations on the locked transponder +--PARAMS IN :: Handle ==>Front End Handle +--PARAMS OUT :: pInfo ==> Informations (BER,C/N,power ...) +--RETURN :: Error (if any) +--***************************************************/ +FE_STB0899_Error_t FE_STB0899_GetSignalInfo(FE_STB0899_Handle_t Handle, FE_STB0899_SignalInfo_t *pInfo) +{ + FE_STB0899_Error_t st_error = FE_NO_ERROR; + FE_STB0899_InternalParams_t *pParams = NULL; + + pParams = (FE_STB0899_InternalParams_t *) Handle; + + if(pParams != NULL) + { + switch(pParams->Standard) + { + case FE_DVBS1_STANDARD: + case FE_DSS_STANDARD: + + pInfo->Locked = ChipGetField(pParams->hDemod, FSTB0899_LOCKEDVIT); + if(pInfo->Locked) + { + pInfo->Power = FE_STB0899_GetRFLevel(pParams->hDemod, &FE_STB0899_RF_LookUp, (STB0899_STANDARD)pParams->Standard); + pInfo->C_N = CarrierGetQuality(pParams->hDemod, &FE_STB0899_CN_LookUp, (STB0899_STANDARD)pParams->Standard); + pInfo->BER = FE_STB0899_GetError(pParams->hDemod, pParams->Standard); + } + break; + + case FE_DVBS2_STANDARD: + pInfo->Locked = ((FE_DVBS2_GetState(pParams->hDemod, 10) == FE_DVBS2_DATAOK) ? 1 : 0); + { + pInfo->C_N = CarrierGetQuality(pParams->hDemod, &FE_STB0899_CN_LookUp, (STB0899_STANDARD)pParams->Standard); + pInfo->Power = FE_STB0899_GetRFLevel(pParams->hDemod, &FE_STB0899_DVBS2RF_LookUp, (STB0899_STANDARD)pParams->Standard); + pInfo->BER = FE_STB0899_GetError(pParams->hDemod, pParams->Standard); + } + break; + } + } + else + st_error = FE_INVALID_HANDLE; + + return st_error; +} + +FE_STB0899_Error_t FE_STB0899_DiseqcSend(FE_STB0899_Handle_t Handle, u8 *Data, u32 NbData) +{ + FE_STB0899_Error_t st_error = FE_NO_ERROR; + FE_STB0899_InternalParams_t *pParams = NULL; + + pParams = (FE_STB0899_InternalParams_t *)Handle; + + if(pParams != NULL) + { + u32 i=0; + + ChipSetField(pParams->hDemod, FSTB0899_DISPRECHARGE, 1); + while(ihDemod, FSTB0899_FIFOPARITYFAIL)); + /*send byte to FIFO::WARNING don't use set field!!*/ + ChipSetOneRegister(pParams->hDemod, RSTB0899_DISFIFO, Data[i]); + i++; + } + ChipSetField(pParams->hDemod, FSTB0899_DISPRECHARGE, 0); + } + else + st_error = FE_INVALID_HANDLE; + + return st_error; +} + +/***************************************************** +--FUNCTION :: FE_STB0899_Set22KHZContinues +--ACTION :: Initialize DiseqC +--PARAMS IN :: Handle ==> Front End Handle + ToneOn ==> 22 KHz on Off +--PARAMS OUT :: RxFreq ==> None. +--RETURN :: Error (if any) +--***************************************************/ +FE_STB0899_Error_t FE_STB0899_Set22KHZContinues(FE_STB0899_Handle_t Handle, BOOL ToneOn) +{ + u32 mclk, div; + FE_STB0899_Error_t st_error = FE_NO_ERROR; + FE_STB0899_InternalParams_t *pParams = NULL; + + pParams = (FE_STB0899_InternalParams_t *)Handle; + if(pParams != NULL) + { + switch(ToneOn) + { + case SEC_TONE_ON: + mclk=FE_STB0899_GetMclkFreq(pParams->hDemod, pParams->Quartz); + div = (mclk / 100) / (2 * 32 * 22 * 4); + div = (div + 5) / 10; + /*Route DiseqC Tx pin to AuxClock0 */ + ChipSetOneRegister(pParams->hDemod, RSTB0899_DISEQCOCFG, 0x66); + ChipSetField(pParams->hDemod, FSTB0899_ACRPRESC, 3); + ChipSetField(pParams->hDemod, FSTB0899_ACRDIV1, div); + break; + + case SEC_TONE_OFF: + /*Set Diseqc pin to general diseq mod*/ + ChipSetOneRegister(pParams->hDemod, RSTB0899_DISEQCOCFG, 0x20); + break; + } + } + else + st_error = FE_INVALID_HANDLE; + + return st_error; +} + +STCHIP_Error_t STB0899_RepeaterFn(STCHIP_Handle_t hChip, BOOL State) +{ + STCHIP_Error_t ch_error = CHIPERR_NO_ERROR; + + if(hChip != NULL) + { + if(State == TRUE) + ChipSetField(hChip, FSTB0899_I2CTON, 1); + } + + return ch_error; +} + + + + + + diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/frontends/stb0899_drv.h kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/stb0899_drv.h --- kernel-2.6.24.4-orig/drivers/media/dvb/frontends/stb0899_drv.h 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/stb0899_drv.h 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,262 @@ +#ifndef STB0899_DRV_H +#define STB0899_DRV_H + +#include "stb0899.h" +#include "stb0899_common.h" +#include "stb0899_dvbs2util.h" +#include "stb0899_util.h" +#include "stb0899_init.h" +#include "stb0899_tuner.h" + +/**************************************************************** + COMMON STRUCTURES AND TYPEDEF +****************************************************************/ +typedef enum +{ + FE_NO_ERROR, + FE_INVALID_HANDLE, + FE_ALLOCATION, + FE_BAD_PARAMETER, + FE_ALREADY_INITIALIZED, + FE_I2C_ERROR, + FE_SEARCH_FAILED, + FE_TRACKING_FAILED, + FE_TERM_FAILED +} FE_STB0899_Error_t; + +typedef enum +{ + FE_MOD_BPSK, + FE_MOD_QPSK, + FE_MOD_OQPSK, + FE_MOD_8PSK +} FE_STB0899_Modulation_t; + +typedef enum +{ + FE_IQ_AUTO, + FE_IQ_NORMAL, + FE_IQ_SWAPPED +}FE_STB0899_IQ_Inversion; + +typedef enum +{ + FE_1_2 =13, + FE_2_3 =18, + FE_3_4 =21, + FE_5_6 =24, + FE_6_7 =25, + FE_7_8 =26 +}FE_STB0899_Rate_t; + +typedef enum +{ + FE_PARALLEL_CLOCK, + FE_SERIAL_MASTER_CLOCK, + FE_SERIAL_VCODIV6_CLOCK +} FE_STB0899_Clock_t; + +typedef enum +{ + FE_PARITY_ON, + FE_PARITY_OFF +} FE_STB0899_DataParity_t; +/* The FEC mode corresponds to the DVB standard */ +typedef enum +{ + FE_DVBS1_STANDARD, + FE_DVBS2_STANDARD, + FE_DSS_STANDARD +} FE_STB0899_CodingStandard_t; + +/*Internal error definitions*/ +typedef enum +{ + FE_IERR_NO, /*no error */ + FE_IERR_I2C, /*I2C error */ + FE_IERR_ZERODIV, /*division by zero*/ + FE_IERR_PARAM, /*wrong parameters*/ + FE_IERR_UNKNOWN /*unknown error */ +} FE_STB0899_ErrorType_t; + +typedef enum +{ + FE_LOC_NOWHERE, /*no location */ + FE_LOC_SRHINIT, /*in SearchInit */ + FE_LOC_SRHRUN, /*in SearchRun */ + FE_LOC_SRHTERM, /*in SearchTerm */ + FE_LOC_SETSR, /*in SetSymbolRate*/ + FE_LOC_TIMTCST, /*in TimingTimeConstant */ + FE_LOC_DERTCST, /*in DerotTimeConstant*/ + FE_LOC_DATTCST, /*in DataTimeConstant*/ + FE_LOC_CHKTIM, /*in CheckTiming*/ + FE_LOC_SRHCAR, /*in SearchCarrier*/ + FE_LOC_SRHDAT, /*in SearchData */ + FE_LOC_CHKRNG, /*in CheckRange */ + FE_LOC_SELLPF /*in SelectLPF */ +} FE_STB0899_Location_t; + +/**************************************************************** + INIT STRUCTURES + structure passed to the FE_STB0899_Init() function +****************************************************************/ + typedef struct +{ + STB0899_InitParams_t *STB0899Init; /* parameters to pass to initialize the STB0899 */ + TUNER_InitParams_t *TunerInit; /* parameters to pass to initialize the Tuner*/ + STCHIP_Info_t *LnbInit; /* parameters to pass to initialize the LNBP21*/ + FE_STB0899_CodingStandard_t Standard; /* standard used : DVBS1,DVBS2*/ + FE_STB0899_Clock_t Clock; /* Clock settings */ + FE_STB0899_DataParity_t Parity; /* parity of the data*/ +} FE_STB0899_InitParams_t; + +/**************************************************************** + SEARCH STRUCTURES + ****************************************************************/ +typedef struct +{ + u32 Frequency; /* transponder frequency (in KHz)*/ + u32 SymbolRate; /* transponder symbol rate (in bds)*/ + u32 SearchRange; /* range of the search (in Hz) */ + FE_STB0899_Modulation_t Modulation; /* modulation*/ + FE_STB0899_CodingStandard_t Standard; /*Dvb dvbs2*/ + FE_STB0899_IQ_Inversion IQ_Inversion; /* IQ spectrum search for DVBS2*/ +} FE_STB0899_SearchParams_t; + +typedef struct +{ + BOOL Locked; /* Transponder found */ + u32 Frequency; /* found frequency*/ + u32 SymbolRate; /* founded symbol rate*/ + FE_STB0899_Rate_t Rate; /* puncture rate for DVBS1*/ + FE_DVBS2_ModCod_t ModCode; /* found modecode only for DVBS2*/ + BOOL Pilots; /* pilots found*/ + FE_DVBS2_FRAME FrameLength; /* found frame length*/ +} FE_STB0899_SearchResult_t; + +/*********************************************************** + INFO STRUCTURE +***********************************************************/ +typedef struct +{ + BOOL Locked; /* Transponder locked*/ + u32 Frequency; /* transponder frequency (in KHz)*/ + u32 SymbolRate; /* transponder symbol rate (in Mbds)*/ + FE_STB0899_Modulation_t Modulation; /* modulation*/ + FE_STB0899_Rate_t Rate; /* puncture rate for DVBS1 mode */ + FE_DVBS2_ModCod_t ModCode; /* only for DVBS2*/ + BOOL Pilots; /* Pilots on/off only for DVB-S2*/ + FE_DVBS2_FRAME FrameLength; /* found frame length*/ + S32 Power; /* Power of the RF signal (dBm)*/ + u32 C_N; /* Carrier to noise ratio*/ + u32 BER; /* Bit error rate*/ + S16 SpectralInv; /* I,Q Inversion */ +} FE_STB0899_SignalInfo_t; + +typedef struct +{ + FE_STB0899_ErrorType_t Type; /* Error type */ + FE_STB0899_Location_t Location; /* Error location*/ +} FE_STB0899_InternalError_t; + +typedef struct +{ + /*DVB Internal Params*/ + u32 Frequency; /*Transponder frequency (KHz)*/ + FE_STB0899_SIGNALTYPE_t SignalType; /*Type of founded signal*/ + FE_STB0899_Rate_t PunctureRate; /*Puncture rate found*/ + u32 SymbolRate; /*Symbol rate (Bds)*/ + + /*DVBS2 Internal Params*/ + FE_DVBS2_State DVBS2SignalType; + u32 DVBS2SymbolRate; /*founded Symbol rate (Bds)*/ + FE_DVBS2_ModCod_t ModCode; /*founded ModCod*/ + BOOL Pilots; /*Pilots founded*/ + FE_DVBS2_FRAME FrameLength; /* found frame length*/ +} FE_STB0899_InternalResults_t; + +/*Internal param structure*/ +typedef struct +{ + STCHIP_Handle_t hDemod; /*Handle to the chip*/ + TUNER_Handle_t hTuner; /*Handle to the tuner*/ + STCHIP_Handle_t hLnb; /*Handle to the chip*/ + + FE_STB0899_CodingStandard_t Standard; + S32 Quartz; /*Quartz frequency (Hz) */ + S32 Frequency, /*Current tuner frequency (KHz) */ + BaseFreq, /*Start tuner frequency (KHz) */ + SubRange, /*Current sub range (Hz) */ + TunerStep, /*Tuner step (Hz) */ + TunerOffset, /*Tuner offset relative to the carrier (Hz) */ + TunerBW; /*Current bandwidth of the tuner (Hz) */ + + /*DVBS1 Params*/ + FE_STB0899_SIGNALTYPE_t State; /*Current state of the search algorithm */ + FE_DVBS2_State DVBS2State; + + S32 SymbolRate, /*Symbol rate (Bds) */ + MasterClock, /*Master clock frequency (Hz) */ + Mclk, /*Divider factor for masterclock (binary value) */ + SearchRange, /*Search range (Hz) */ + RollOff; /*Current RollOff of the filter (x100) */ + + S16 DerotFreq, /*Current frequency of the derotator (Hz) */ + DerotPercent, /*Derotator step (in thousands of symbol rate) */ + DerotStep, /*Derotator step (binary value) */ + Direction, /*Current search direction */ + Tagc1, /*Agc1 time constant (ms) */ + Tagc2, /*Agc2 time constant (ms) */ + Ttiming, /*Timing loop time constant (ms) */ + Tderot, /*Derotator time constant (ms) */ + Tdata, /*Data recovery time constant (ms) */ + SubDir; /*Direction of the next sub range */ + + /*DVBS2 Params*/ + S32 DVBS2SymbolRate, /*Symbol rate (Bds) */ + AgcGain, /* RF AGC Gain */ + AveFrameCoarse, + AveFramefine, + AgcThreshold, + FreqRange, + CenterFreq, + AveFrameCoarseAcq, + AveFramefineAcq, + AveFrameCoarseTrq, + AveFramefineTrq; + + S16 AutoReacq, + TracklockSel, + Zigzag, + StepSize; + + FE_STB0899_IQ_Inversion SpectralInv; + FE_DVBS2_Mode_t mod; + FE_DVBS2_AcqMode AcqMode; + FE_DVBS2_RRCAlpha_t RrcAlpha; + + /*Result and error */ + FE_STB0899_InternalResults_t Results; /* Results of the search*/ + FE_STB0899_InternalError_t Inl_Error; /* Last error encountered*/ +}FE_STB0899_InternalParams_t; + +/**************************************************************** + API FUNCTIONS +****************************************************************/ + +FE_STB0899_Handle_t FE_STB0899_Init(FE_STB0899_InitParams_t *pInit); + +FE_STB0899_Error_t FE_STB0899_Search(FE_STB0899_Handle_t Handle, FE_STB0899_SearchParams_t * pParams, FE_STB0899_SearchResult_t * pResult); + +FE_STB0899_Error_t FE_STB0899_GetSignalInfo(FE_STB0899_Handle_t Handle, FE_STB0899_SignalInfo_t * pInfo); + +FE_STB0899_Error_t FE_STB0899_DiseqcSend(FE_STB0899_Handle_t Handle, u8 *Data, u32 NbData); + +FE_STB0899_Error_t FE_STB0899_Set22KHZContinues(FE_STB0899_Handle_t Handle, BOOL ToneOn); + +FE_STB0899_Error_t FE_STB0899_Term(FE_STB0899_Handle_t Handle); + +FE_STB0899_Error_t FE_STB0899_SetMclk(FE_STB0899_Handle_t Handle, u32 Mclk, u32 ExtClk); + +#endif + diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/frontends/stb0899_dvbs2util.c kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/stb0899_dvbs2util.c --- kernel-2.6.24.4-orig/drivers/media/dvb/frontends/stb0899_dvbs2util.c 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/stb0899_dvbs2util.c 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,711 @@ + +#include "stb0899_dvbs2util.h" +#include "stb0899_init.h" +#include "stb0899_util.h" + + +/*Set carrier freq (mhz) masterclock mhz*/ +static void FE_DVBS2_SetCarrierFreq(STCHIP_Handle_t hChip, S32 CarrierFreq, u32 MasterClock) +{ + S32 crlNomFreq; + + crlNomFreq=(PowOf2(CRL_NCO_BITS))/MasterClock; + crlNomFreq*=CarrierFreq; + ChipSetField(hChip,FSTB0899_CRLNOM_FREQ,crlNomFreq); +} + +static u32 DVBS2CalclSymbRate(u32 SymbolRate, u32 MasterClock) +{ + u32 decimRatio, + decimRate, + decimation, + remain, + intval, + btrNomFreq; + + decimRatio = (MasterClock*2) / (5 * SymbolRate); + decimRatio = (decimRatio == 0) ? 1 : decimRatio; + decimRate = Log2Int(decimRatio); + decimation = 1 << decimRate; + MasterClock /= 1000; /* for integer Caculation*/ + SymbolRate /= 1000; /* for integer Caculation*/ + + if(decimation <= 4) + { + intval = (decimation*PowOf2(BTR_NCO_BITS-1)) / MasterClock; + remain = (decimation*PowOf2(BTR_NCO_BITS-1)) % MasterClock; + } + else + { + intval = PowOf2(BTR_NCO_BITS-1) / (MasterClock/100) * decimation / 100; + remain = (decimation * PowOf2(BTR_NCO_BITS-1)) % MasterClock; + } + btrNomFreq =(intval*SymbolRate) + ((remain*SymbolRate) / MasterClock); + + return btrNomFreq; +} + +static u32 CalcCorrection(u32 SymbolRate, u32 MasterClock) +{ + u32 decimRatio, correction; + + decimRatio = (MasterClock*2) / (5 * SymbolRate); + decimRatio = (decimRatio == 0) ? 1 : decimRatio; + + MasterClock/=1000; /* for integer Caculation*/ + SymbolRate/=1000; /* for integer Caculation*/ + correction=(512 * MasterClock) / (2 * decimRatio * SymbolRate); + + return correction; +} + +/* Sets the symbol rate to demodulate (valid range 1.0 MHz - 45.0 MHz */ +static void FE_DVBS2_SetSymbolRate(STCHIP_Handle_t hChip, u32 SymbolRate, u32 MasterClock) +{ + u32 decimRatio, + decimRate, + winSel, + decimation, + fSymovSr, + btrNomFreq, + correction, + freqAdjScl, + bandLimit, + decimcntrlreg; + + /*set decimation to 1*/ + decimRatio = (MasterClock*2) / (5 * SymbolRate); + decimRatio = (decimRatio == 0) ? 1 : decimRatio; + decimRate = Log2Int(decimRatio); + + winSel=0; + if(decimRate >= 5) + winSel = decimRate - 4; + + decimation = (1 << decimRate); + + /* (FSamp/Fsymbol *100) for integer Caculation */ + fSymovSr=MasterClock / ((decimation*SymbolRate) / 1000); + + /* don't band limit signal going into btr block*/ + if(fSymovSr<=2250) + bandLimit=1; + else + bandLimit=0; /* band limit signal going into btr block*/ + + decimcntrlreg=((winSel << 3) & 0x18) + ((bandLimit << 5) & 0x20) + (decimRate & 0x7); + ChipSetOneRegister(hChip, RSTB0899_DECIMCNTRL, decimcntrlreg); + + if(fSymovSr<=3450) + ChipSetOneRegister(hChip, RSTB0899_ANTIALIASSEL, 0); + else if(fSymovSr<=4250) + ChipSetOneRegister(hChip, RSTB0899_ANTIALIASSEL, 1); + else + ChipSetOneRegister(hChip, RSTB0899_ANTIALIASSEL, 2); + + btrNomFreq = DVBS2CalclSymbRate(SymbolRate, MasterClock); + ChipSetOneRegister(hChip, RSTB0899_BTRNOMFREQ, btrNomFreq); + + correction = CalcCorrection(SymbolRate, MasterClock); + ChipSetField(hChip, FSTB0899_BTRFREQ_CORR, correction); + + /* scale UWP+CSM frequency to sample rate*/ + freqAdjScl = SymbolRate / (MasterClock / 4096); + ChipSetOneRegister(hChip, RSTB0899_FREQADJSCALE, freqAdjScl); +} + +/* Sets the Bit Timing loop bandwidth as a percentage of the symbol rate */ +static void FE_DVBS2_SetBtrLoopBW(STCHIP_Handle_t hChip, FE_DVBS2_LoopBW_Params_t LoopBW) +{ + S32 decimRatio, + decimRate, + kbtr1Rshft, + kbtr1, + kbtr0Rshft, + kbtr0, + kbtr2Rshft, + kDirectShift, + kIndirectShift; + + u32 decimation, + K, + wn, + kDirect, + kIndirect; + + decimRatio = (LoopBW.MasterClock * 2) / (5 * LoopBW.SymbolRate); + decimRatio = (decimRatio == 0) ? 1 : decimRatio; + decimRate = Log2Int(decimRatio); + decimation = (1 << decimRate); + + LoopBW.SymPeakVal = LoopBW.SymPeakVal * 576000; + + K = PowOf2(BTR_NCO_BITS) / (LoopBW.MasterClock / 1000); + K *= (LoopBW.SymbolRate / 1000000) * decimation; /*k=k 10^-8*/ + + K = LoopBW.SymPeakVal / K; + + if(K != 0) + { + /*wn =wn 10^-8*/ + wn = (4 * LoopBW.Zeta * LoopBW.Zeta) + 1000000; + wn =(2 * (LoopBW.LoopBwPercent * 1000) * 40 * LoopBW.Zeta) / wn; + + kIndirect = (wn * wn) / K; + kIndirect = kIndirect; /*kindirect = kindirect 10^-6*/ + + kDirect = (2 * wn * LoopBW.Zeta) / K; /*kDirect = kDirect 10^-2*/ + kDirect *= 100; + + kDirectShift = Log2Int(kDirect) - Log2Int(10000) - 2; + kbtr1Rshft = (-1 * kDirectShift) + BTR_GAIN_SHIFT_OFFSET; + kbtr1 = kDirect / PowOf2(kDirectShift); + kbtr1 /= 10000; + + kIndirectShift = Log2Int(kIndirect + 15) - 20; + kbtr0Rshft = (-1 * kIndirectShift) + BTR_GAIN_SHIFT_OFFSET; + kbtr0 = kIndirect * PowOf2(-kIndirectShift); + kbtr0 /= 1000000; + + kbtr2Rshft = 0; + if( kbtr0Rshft > 15) + { + kbtr2Rshft = kbtr0Rshft - 15; + kbtr0Rshft = 15; + } + + ChipSetFieldImage(hChip, FSTB0899_KBTR0_RSHFT, kbtr0Rshft); + ChipSetFieldImage(hChip, FSTB0899_KBTR0, kbtr0); + ChipSetFieldImage(hChip, FSTB0899_KBTR1_RSHT, kbtr1Rshft); + ChipSetFieldImage(hChip, FSTB0899_KBTR1, kbtr1); + ChipSetFieldImage(hChip, FSTB0899_KBTR2_RSHT, kbtr2Rshft); + + ChipSetRegisters(hChip, RSTB0899_BTRLOOPGAIN, 1); + } + else + ChipSetOneRegister(hChip, RSTB0899_BTRLOOPGAIN, 0xc4c4f); +} + +/* Initializes the BTR loop hardware */ +static void FE_DVBS2_BtrInit(STCHIP_Handle_t hChip) +{ + /* set enable BTR loopback*/ + ChipSetFieldImage(hChip, FSTB0899_INTRP_PHS_SENS, 1); + ChipSetFieldImage(hChip, FSTB0899_BTRERR_ENA, 1); + ChipSetRegisters(hChip, RSTB0899_BTRCNTRL, 1); + + /* fix btr freq accum at 0*/ + ChipSetOneRegister(hChip, RSTB0899_BTRFREQINIT, 0x10000000); + ChipSetOneRegister(hChip, RSTB0899_BTRFREQINIT, 0x00000000); + + /* fix btr freq accum at 0*/ + ChipSetOneRegister(hChip, RSTB0899_BTRPHSINIT, 0x10000000); + ChipSetOneRegister(hChip, RSTB0899_BTRPHSINIT, 0x00000000); +} + +static void FE_DVBS2_Reset(STCHIP_Handle_t hChip) +{ + u32 imbHold, + dcHold; + + int i=0; + + ChipSetFieldImage(hChip, FSTB0899_IF_LDGAININIT, 1); + ChipSetRegisters(hChip, RSTB0899_IFAGCCNTRL, 1); + + ChipSetFieldImage(hChip, FSTB0899_BBLDGAIN_INIT, 1); + ChipSetRegisters(hChip, RSTB0899_BBAGCCNTRL, 1); + + ChipSetFieldImage(hChip, FSTB0899_CRLPHSINIT31, 1); + ChipSetRegisters(hChip, RSTB0899_CRLPHSINIT, 1); + + ChipSetFieldImage(hChip, FSTB0899_CRLFREQINIT31, 1); + ChipSetRegisters(hChip, RSTB0899_CRLFREQINIT, 1); + + ChipSetFieldImage(hChip, FSTB0899_BTRID_PHASEINIT, 1); + ChipSetRegisters(hChip, RSTB0899_BTRPHSINIT, 1); + + ChipSetFieldImage(hChip, FSTB0899_BTRID_FREQINIT, 1); + ChipSetRegisters(hChip, RSTB0899_BTRFREQINIT, 1); + + imbHold=ChipGetOneRegister(hChip, RSTB0899_IMBCNTRL); + + ChipSetFieldImage(hChip, FSTB0899_IMB_COMP, 0); + ChipSetRegisters(hChip, RSTB0899_IMBCNTRL, 1); + + dcHold=ChipGetOneRegister(hChip, RSTB0899_DMDCNTRL); + + ChipSetFieldImage(hChip, FSTB0899_DC_COMP, 0); + ChipSetRegisters(hChip, RSTB0899_DMDCNTRL, 1); + + ChipSetFieldImage(hChip, FSTB0899_CRL_CLR_PHSERR, 1); + ChipSetRegisters(hChip, RSTB0899_CRLCNTRL, 1); + + /*WAIT_N_MS(2);*/ + ChipSetFieldImage(hChip, FSTB0899_IF_LDGAININIT, 0); + ChipSetRegisters(hChip, RSTB0899_IFAGCCNTRL, 1); + + /*whait for IF AGC lock*/ + while((ChipGetField(hChip, FSTB0899_IF_AGCLOCK) != 1) && (i < 30)) + i++; + + ChipSetFieldImage(hChip, FSTB0899_BTRID_PHASEINIT, 0); + ChipSetRegisters(hChip, RSTB0899_BTRPHSINIT, 1); + + /*WAIT_N_MS(2);*/ + ChipSetFieldImage(hChip, FSTB0899_CRLPHSINIT31, 0); + ChipSetRegisters(hChip, RSTB0899_CRLPHSINIT, 1); + + ChipSetFieldImage(hChip, FSTB0899_CRLFREQINIT31, 0); + ChipSetRegisters(hChip, RSTB0899_CRLFREQINIT, 1); + + ChipSetFieldImage(hChip, FSTB0899_BBLDGAIN_INIT, 0); + ChipSetRegisters(hChip, RSTB0899_BBAGCCNTRL, 1); + + ChipSetFieldImage(hChip, FSTB0899_BTRID_FREQINIT, 0); + ChipSetRegisters(hChip, RSTB0899_BTRFREQINIT, 1); + + ChipSetOneRegister(hChip, RSTB0899_IMBCNTRL,imbHold | 1); + ChipSetOneRegister(hChip, RSTB0899_DMDCNTRL,dcHold | 14); + + ChipSetFieldImage(hChip, FSTB0899_CRL_CLR_PHSERR, 0); + ChipSetRegisters(hChip, RSTB0899_CRLCNTRL, 1); +} + +/* config UWP */ +static void FE_DVBS2_ConfigUWP(STCHIP_Handle_t hChip, FE_DVBS2_UWPConfig_Params_t UWPparams) +{ + /*Set Fields imgae value*/ + ChipSetFieldImage(hChip, FSTB0899_UWP_ESN0_AVE, UWPparams.EsNoAve); + ChipSetFieldImage(hChip, FSTB0899_UWP_ESN0_QUANT, UWPparams.EsNoQuant); + ChipSetFieldImage(hChip, FSTB0899_UWP_THRESHOLD_SOF, UWPparams.ThresholdSof); + ChipSetFieldImage(hChip, FSTB0899_FE_COARSE_TRK, UWPparams.AveFramesCoarse); + ChipSetFieldImage(hChip, FSTB0899_FE_FINE_TRK, UWPparams.AveframesFine); + ChipSetFieldImage(hChip, FSTB0899_UWP_MISS_THRESHOLD, UWPparams.MissThreshold); + ChipSetFieldImage(hChip, FSTB0899_UWP_THRESHOLD_ACQ, UWPparams.ThresholdAcq); + ChipSetFieldImage(hChip, FSTB0899_UWP_THRESHOLD_TRACK, UWPparams.ThresholdTrack); + + /*write values to registers*/ + ChipSetRegisters(hChip, RSTB0899_UWPCNTRL1, 1); + ChipSetRegisters(hChip, RSTB0899_UWPCNTRL2, 1); + ChipSetRegisters(hChip, RSTB0899_UWPCNTRL3, 1); + + ChipSetOneRegister(hChip, RSTB0899_SOFSRCHTO, UWPparams.SofSearchTimeout); +} + +/* start UWP */ +static void FE_DVBS2_StartUWP(STCHIP_Handle_t hChip) +{ + /* write a 1 to the start reg */ + ChipSetFieldImage(hChip, FSTB0899_UWP_START, 1); + ChipSetRegisters(hChip, RSTB0899_UWPCNTRL1, 1); + + /* write a 0 to the start reg */ + ChipSetField(hChip, FSTB0899_UWP_START, 0); + ChipSetRegisters(hChip, RSTB0899_UWPCNTRL1, 1); +} + +/* config CSM with internal stored parameters */ +static void FE_DVBS2_AutoConfigCSM(STCHIP_Handle_t hChip) +{ + /* to auto=config write a 1 to auto_param register */ + /*Set filed image value*/ + ChipSetFieldImage(hChip, FSTB0899_AUTO_PARAM, 1); + /*write value to the register*/ + ChipSetRegisters(hChip, RSTB0899_CSMCNTRL1, 1); +} + +static void FE_DVBS2_ManualConfigCSM(STCHIP_Handle_t hChip,FE_DVBS2_CSMConfig_Params_t CSMParams) +{ + /* to manually config write a 0 to auto_param register*/ + + /*Set filed image value*/ + ChipSetFieldImage(hChip, FSTB0899_AUTO_PARAM, 0); + /*write value to the register*/ + ChipSetRegisters(hChip, RSTB0899_CSMCNTRL1, 1); + + /*configure other registers*/ + ChipSetFieldImage(hChip, FSTB0899_CSM_DVT_TABLE, CSMParams.DvtTable); + ChipSetFieldImage(hChip, FSTB0899_CSM_TOW_PASS, CSMParams.TwoPass); + ChipSetFieldImage(hChip, FSTB0899_CSM_AGC_GAIN, CSMParams.AgcGain); + ChipSetFieldImage(hChip, FSTB0899_CSM_AGC_SHIFT, CSMParams.AgcShift); + ChipSetFieldImage(hChip, FSTB0899_FE_LOOP_SHIFT, CSMParams.FeLoopShift); + ChipSetFieldImage(hChip, FSTB0899_CSM_GAMMA_ACQ, CSMParams.GammaAcq); + ChipSetFieldImage(hChip, FSTB0899_CSM_GAMMA_RHOACQ, CSMParams.GammaRhoAcq); + ChipSetFieldImage(hChip, FSTB0899_CSM_GAMMA_TRACK, CSMParams.GammaTrack); + ChipSetFieldImage(hChip, FSTB0899_CSM_GAMMA_RHOTRACK, CSMParams.GammaRhoTrack); + ChipSetFieldImage(hChip, FSTB0899_LOCK_COUNT_THRESHOLD, CSMParams.LockCountThreshold); + ChipSetFieldImage(hChip, FSTB0899_PHASE_DIFF_THRESHOLD, CSMParams.PhaseDiffThreshold); + + ChipSetRegisters(hChip, RSTB0899_CSMCNTRL1, 1); + ChipSetRegisters(hChip, RSTB0899_CSMCNTRL2, 1); + ChipSetRegisters(hChip, RSTB0899_CSMCNTRL3, 1); + ChipSetRegisters(hChip, RSTB0899_CSMCNTRL4, 1); +} + +/* for future regarding QPSK w/Pilots over sampling <=4*/ +void FE_DVBS2_CSMInitialize(STCHIP_Handle_t hChip, int Pilots, FE_DVBS2_ModCod_t ModCode, u32 SymbolRate, u32 MasterClock) +{ + FE_DVBS2_CSMConfig_Params_t csmParams; + + csmParams.DvtTable = 1; + csmParams.TwoPass = 0; + csmParams.AgcGain = 6; + csmParams.AgcShift = 0; + csmParams.FeLoopShift = 0; + csmParams.PhaseDiffThreshold = 0x80; + + if( ((MasterClock / SymbolRate) <= 4) && (ModCode <= 11) && (Pilots == 1)) + { + switch (ModCode) + { + case FE_QPSK_12: + csmParams.GammaAcq = 25; + csmParams.GammaRhoAcq = 2700; + csmParams.GammaTrack = 12; + csmParams.GammaRhoTrack = 180; + csmParams.LockCountThreshold = 8; + break; + + case FE_QPSK_35: + csmParams.GammaAcq = 38; + csmParams.GammaRhoAcq = 7182; + csmParams.GammaTrack = 14; + csmParams.GammaRhoTrack = 308; + csmParams.LockCountThreshold = 8; + break; + + case FE_QPSK_23: + csmParams.GammaAcq = 42; + csmParams.GammaRhoAcq = 9408; + csmParams.GammaTrack = 17; + csmParams.GammaRhoTrack = 476; + csmParams.LockCountThreshold = 8; + break; + + case FE_QPSK_34: + csmParams.GammaAcq = 53; + csmParams.GammaRhoAcq = 16642; + csmParams.GammaTrack = 19; + csmParams.GammaRhoTrack = 646; + csmParams.LockCountThreshold = 8; + break; + + case FE_QPSK_45: + csmParams.GammaAcq = 53; + csmParams.GammaRhoAcq = 17119; + csmParams.GammaTrack = 22; + csmParams.GammaRhoTrack = 880; + csmParams.LockCountThreshold = 8; + break; + + case FE_QPSK_56: + csmParams.GammaAcq = 55; + csmParams.GammaRhoAcq = 19250; + csmParams.GammaTrack = 23; + csmParams.GammaRhoTrack = 989; + csmParams.LockCountThreshold = 8; + break; + + case FE_QPSK_89: + csmParams.GammaAcq = 60; + csmParams.GammaRhoAcq = 24240; + csmParams.GammaTrack = 24; + csmParams.GammaRhoTrack = 1176; + csmParams.LockCountThreshold = 8; + break; + + case FE_QPSK_910: + csmParams.GammaAcq = 66; + csmParams.GammaRhoAcq = 29634; + csmParams.GammaTrack = 24; + csmParams.GammaRhoTrack = 1176; + csmParams.LockCountThreshold = 8; + break; + + default: + csmParams.GammaAcq = 66; + csmParams.GammaRhoAcq = 29634; + csmParams.GammaTrack = 24; + csmParams.GammaRhoTrack = 1176; + csmParams.LockCountThreshold = 8; + break; + } + FE_DVBS2_ManualConfigCSM(hChip, csmParams); + } +} + +/* read csm lock */ +static int FE_DVBS2_GetCSMLock(STCHIP_Handle_t hChip, int TimeOut) +{ + int Time=0, + CSMLocked=0; + + while((!CSMLocked) && (Time < TimeOut)) + { + CSMLocked = ChipGetField(hChip, FSTB0899_CSM_LOCK); + Time++; + } + + return CSMLocked; +} + +/* read uwp_state */ +static int FE_DVBS2_GetUWPstate(STCHIP_Handle_t hChip, int TimeOut) +{ + int Time=0, + lock=0, + locked=0; + + while((Time < TimeOut) && (lock == 0)) + { + lock = ChipGetField(hChip, FSTB0899_UWP_LOCK); + Time++; + } + if(lock) + locked = 1; + + return locked; +} + +static int FE_DVBS2_GetDataLock(STCHIP_Handle_t hChip, int TimeOut) +{ + int Time = 0, + DataLocked = 0; + + while((!DataLocked) && (Time < TimeOut)) + { + DataLocked = ChipGetField(hChip, FSTB0899_LOCK); + Time++; + } + + return DataLocked; +} + +FE_DVBS2_State FE_DVBS2_GetState(STCHIP_Handle_t hChip,int Timeout) +{ + int tout, i = 0; + FE_DVBS2_State state = FE_DVBS2_NOAGC; + + tout = Timeout; + do + { + if(FE_DVBS2_GetCSMLock(hChip, 1) != TRUE) + state = FE_DVBS2_NOCARRIER; + else + if((FE_DVBS2_GetUWPstate(hChip, 1) != TRUE)) + state = FE_DVBS2_NOUWP; + else + if(FE_DVBS2_GetDataLock(hChip, 1) != TRUE) + state = FE_DVBS2_NODATA; + else + state = FE_DVBS2_DATAOK; + + WAIT_N_MS(1); + i++; + }while((i < tout) && (state != FE_DVBS2_DATAOK)); + + return state; +} + +/* read modecode */ +u32 FE_DVBS2_GetModCod(STCHIP_Handle_t hChip) +{ + return(ChipGetField(hChip,FSTB0899_UWP_DECODED_MODCODE) >> 2); +} + + +/* read EsNo */ +S32 FE_DVBS2_GetUWPEsNo(STCHIP_Handle_t hChip,S32 Quant) +{ + u32 tempus; + + tempus = ChipGetField(hChip,FSTB0899_ESN0_ESR); + return tempus; /* to convert value to db tempus=(10*log10(tempus)/(quant^2)*/ + /* with quant = UWP_ESN0_QUANT field value */ +} + +/***************************************************** +--FUNCTION :: FE_DVBS2_CarrierWidth +--ACTION :: Compute the width of the carrier +--PARAMS IN :: SymbolRate->Symbol rate of the carrier (Kbauds or Mbauds) +-- RollOff ->Rolloff * 100 +--PARAMS OUT :: NONE +--RETURN :: Width of the carrier (KHz or MHz) +--***************************************************/ +long FE_DVBS2_CarrierWidth(long SymbolRate, FE_DVBS2_RRCAlpha_t Alpha) +{ + long RollOff = 0; + + switch(Alpha) + { + case RRC_20: + RollOff = 20; + break; + case RRC_25: + RollOff = 25; + break; + case RRC_35: + RollOff = 35; + break; + } + return (SymbolRate + (SymbolRate * RollOff) / 100); +} + +u32 FE_DVBS2_GetSymbolRate(STCHIP_Handle_t hChip,u32 MasterClock) +{ + u32 bTrNomFreq, + symbolRate, + decimRate, + intval1,intval2; + int div1, div2, rem1, rem2; + + div1 = BTR_NCO_BITS/2; + div2 = BTR_NCO_BITS-div1-1; + + bTrNomFreq = ChipGetOneRegister(hChip,RSTB0899_BTRNOMFREQ); + decimRate = ChipGetField(hChip,FSTB0899_DECIM_RATE); + decimRate = PowOf2(decimRate); + + intval1 = MasterClock/PowOf2(div1); + intval2 = bTrNomFreq/PowOf2(div2); + + /*symbrate = (btrnomfreq_register_val*MasterClock)/2^(27+decim_rate_field) */ + rem1 = MasterClock%PowOf2(div1); + rem2 = bTrNomFreq%PowOf2(div2); + symbolRate = (intval1*intval2)+((intval1*rem2)/PowOf2(div2))+((intval2*rem1)/PowOf2(div1)); + symbolRate /= decimRate; + + return symbolRate; +} + +void FE_DVBS2_InitialCalculations(STCHIP_Handle_t hChip, FE_STB0899_DVBS2_InitParams_t *InitParams) +{ + FE_DVBS2_UWPConfig_Params_t uwpParams; + FE_DVBS2_LoopBW_Params_t loopBW; + + uwpParams.EsNoAve = ESNO_AVE; + uwpParams.EsNoQuant = ESNO_QUANT; + uwpParams.AveFramesCoarse = InitParams->AveFrameCoarse; + uwpParams.AveframesFine = InitParams->AveFramefine; + uwpParams.MissThreshold = MISS_THRESHOLD; + uwpParams.ThresholdAcq = UWP_THRESHOLD_ACQ; + uwpParams.ThresholdTrack = UWP_THRESHOLD_TRACK; + uwpParams.ThresholdSof = UWP_THRESHOLD_SOF; + uwpParams.SofSearchTimeout = SOF_SEARCH_TIMEOUT; + + loopBW.LoopBwPercent = 60; + loopBW.SymbolRate = InitParams->SymbolRate; + loopBW.MasterClock = InitParams->MasterClock; + loopBW.Mode = InitParams->ModeMode; + loopBW.Zeta = 707; + loopBW.SymPeakVal = InitParams->AgcThreshold;/**5.76*/ + + /* config uwp and csm */ + FE_DVBS2_ConfigUWP(hChip, uwpParams); + FE_DVBS2_AutoConfigCSM(hChip); + + /* initialize BTR */ + FE_DVBS2_SetSymbolRate(hChip, InitParams->SymbolRate, InitParams->MasterClock); + FE_DVBS2_SetBtrLoopBW(hChip, loopBW); + FE_DVBS2_BtrInit(hChip); + + /* enable frequency adjustment and set spectral inversion */ + ChipSetOneRegister(hChip, RSTB0899_DMDCNTRL2, (2 | (InitParams->SpectralInv << 2))); + + /* disable CRL */ + ChipSetOneRegister(hChip, RSTB0899_CRLFREQINIT, 1 << 30); + ChipSetOneRegister(hChip, RSTB0899_CRLLOOPGAIN, 0); + ChipSetOneRegister(hChip, RSTB0899_CRLPHSINIT, 1 << 30); + ChipSetOneRegister(hChip, RSTB0899_CRLPHSINIT, 0); +} + +void FE_DVBS2_Reacquire(STCHIP_Handle_t hChip, FE_DVBS2_ReacquireParams_t * ReacquireParams) +{ + S32 numSteps, + freqStepSize, + acqcntrl2; + + /*disable input buff*/ + ChipSetOneRegister(hChip, RSTB0899_INTBUFCTRL, 0x00); + + /* set demod soft reset*/ + ChipSetOneRegister(hChip, RSTB0899_RESETCNTRL, 0x1); + + FE_DVBS2_Reset(hChip); + /*release demod soft reset */ + + ChipSetOneRegister(hChip, RSTB0899_RESETCNTRL, 0); + + /* reset decoder */ + ChipSetOneRegister(hChip, RSTB0899_LDPCDECRST, 1); + ChipSetOneRegister(hChip, RSTB0899_LDPCDECRST, 0); + + if(ReacquireParams->AcqMode == NO_SEARCH) + { + FE_DVBS2_StartUWP(hChip); + } + else + { + /*numSteps =(ReacquireParams->FreqRange*100)/((ReacquireParams->SymbolRate/1000000)*ReacquireParams->StepSize); + numSteps=(numSteps+5)/10; + freqStepSize =(ReacquireParams->StepSize * (1<<17))/10;*/ + + if(ReacquireParams->SymbolRate / 1000000 >= 15) + freqStepSize = (1 << 17) / 5; + else if(ReacquireParams->SymbolRate/ 1000000 >= 10) + freqStepSize = (1 << 17) / 7; + + else if(ReacquireParams->SymbolRate / 1000000 >= 5) + freqStepSize = (1 << 17) / 10; + else + freqStepSize = (1 << 17) / 3; + + numSteps = (10 * ReacquireParams->FreqRange * (1 << 17)) / (freqStepSize * (ReacquireParams->SymbolRate / 1000000)); + numSteps = (numSteps + 6) / 10; + numSteps = (numSteps == 0) ? 1 : numSteps; + + if(ReacquireParams->Zigzag) + if(numSteps % 2 == 0) + FE_DVBS2_SetCarrierFreq(hChip, ReacquireParams->CenterFreq - (ReacquireParams->StepSize * (ReacquireParams->SymbolRate / 20000000)), (ReacquireParams->MasterClock) / 1000000); + else + FE_DVBS2_SetCarrierFreq(hChip, ReacquireParams->CenterFreq, (ReacquireParams->MasterClock) / 1000000); + else + FE_DVBS2_SetCarrierFreq(hChip, ReacquireParams->CenterFreq - (ReacquireParams->FreqRange / 2),(ReacquireParams->MasterClock) / 1000000); + + /*Set Carrier Search params (zigzag, num steps and freq step size*/ + acqcntrl2 = (ReacquireParams->Zigzag << 25) | (numSteps << 17) | (freqStepSize); + ChipSetOneRegister(hChip, RSTB0899_ACQCNTRL2, acqcntrl2); + + /* Equalizer Init */ + ChipSetFieldImage(hChip, FSTB0899_EQ_INIT, 1); + ChipSetRegisters(hChip, RSTB0899_EQUILIZERINIT, 1); + ChipSetFieldImage(hChip, FSTB0899_EQ_INIT, 0); + ChipSetRegisters(hChip, RSTB0899_EQUILIZERINIT, 1); + + /* Equalizer Disable update */ + ChipSetFieldImage(hChip, FSTB0899_EQ_DISABLE_UPDATE, 0); + ChipSetRegisters(hChip, RSTB0899_EQCNTL, 1); + + /* start acquistion process */ + ChipSetOneRegister(hChip, RSTB0899_ACQUIRETRIG, 1); + ChipSetOneRegister(hChip, RSTB0899_LOCKLOST, 0); + + /*activate input buff*/ + ChipSetOneRegister(hChip, RSTB0899_INTBUFCTRL, 0x0a); + + /*Reset Packet Delin*/ + ChipSetField(hChip, FSTB0899_ALGOSWRST, 1); + ChipSetField(hChip, FSTB0899_ALGOSWRST, 0); + ChipSetField(hChip, FSTB0899_HYSTSWRST, 1); + ChipSetField(hChip, FSTB0899_HYSTSWRST, 0); + ChipSetOneRegister(hChip, RSTB0899_PDELCTRL, 0x4a); + + /*Reset stream merger*/ + ChipSetField(hChip, FSTB0899_FRESRS, 1); + ChipSetField(hChip, FSTB0899_FRESRS, 0); + } +} + + + diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/frontends/stb0899_dvbs2util.h kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/stb0899_dvbs2util.h --- kernel-2.6.24.4-orig/drivers/media/dvb/frontends/stb0899_dvbs2util.h 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/stb0899_dvbs2util.h 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,203 @@ +#ifndef STB0899_DVBS2UTIL_H +#define STB0899_DVBS2UTIL_H + +#include "stb0899_common.h" +#include "stb0899_chip.h" + +#define BTR_NCO_BITS 28 +#define CRL_NCO_BITS 30 + +#define CRL_GAIN_SHIFT_OFFSET 11 +#define BTR_GAIN_SHIFT_OFFSET 15 + +#define ESNO_AVE 3 +#define ESNO_QUANT 32 +#define AVEFRAMES_COARSE 10 +#define AVEFRAMES_FINE 20 +#define MISS_THRESHOLD 6 +#define UWP_THRESHOLD_ACQ 1125 +#define UWP_THRESHOLD_TRACK 758 +#define UWP_THRESHOLD_SOF 1350 +#define SOF_SEARCH_TIMEOUT 1664100 + +typedef enum +{ + CORR_PEAK, + MIN_FREQ_EST, + UWP_LOCK, + FEC_LOCK, + NO_SEARCH +}FE_DVBS2_AcqMode; + +typedef enum +{ + DVBS2_BPSK, + DVBS2_QPSK, + DVBS2_OQPSK, + DVBS2_PSK8 +}FE_DVBS2_Mode_t; + +typedef enum +{ + FE_DUMMY_PLF, + FE_QPSK_14, + FE_QPSK_13, + FE_QPSK_25, + FE_QPSK_12, + FE_QPSK_35, + FE_QPSK_23, + FE_QPSK_34, + FE_QPSK_45, + FE_QPSK_56, + FE_QPSK_89, + FE_QPSK_910, + FE_8PSK_35, + FE_8PSK_23, + FE_8PSK_34, + FE_8PSK_56, + FE_8PSK_89, + FE_8PSK_910, + FE_16APSK_23, + FE_16APSK_34, + FE_16APSK_45, + FE_16APSK_56, + FE_16APSK_89, + FE_16APSK_910, + FE_32APSK_34, + FE_32APSK_45, + FE_32APSK_56, + FE_32APSK_89, + FE_32APSK_910 +}FE_DVBS2_ModCod_t; + +typedef enum +{ + FE_LONG_FRAME, + FE_SHORT_FRAME +}FE_DVBS2_FRAME; + +typedef enum +{ + RRC_20, + RRC_25, + RRC_35 +}FE_DVBS2_RRCAlpha_t; + +typedef enum +{ + FE_DVBS2_NOAGC, + FE_DVBS2_AGCOK, + FE_DVBS2_TIMINGOK, + FE_DVBS2_NOTIMING, + FE_DVBS2_NOCARRIER, + FE_DVBS2_CARRIEROK, + FE_DVBS2_NOUWP, + FE_DVBS2_UWPOK, + FE_DVBS2_NODATA, + FE_DVBS2_DATAOK +}FE_DVBS2_State; + +typedef struct +{ + u32 LoopBwPercent; + u32 SymbolRate; + u32 MasterClock; + FE_DVBS2_Mode_t Mode; + u32 Zeta; + u32 SymPeakVal; +}FE_DVBS2_LoopBW_Params_t; + +typedef struct +{ + u32 Adapt; + u32 AmplImbEstim; + u32 PhsImbEstim; + u32 AmplAdaptLsht; + u32 PhsAdaptLsht; +}FE_DVBS2_ImbCompInit_Params_t; + +typedef struct +{ + S32 EsNoAve, + EsNoQuant, + AveFramesCoarse, + AveframesFine, + MissThreshold, + ThresholdAcq, + ThresholdTrack, + ThresholdSof, + SofSearchTimeout; +}FE_DVBS2_UWPConfig_Params_t; + +typedef struct +{ + S32 DvtTable, + TwoPass, + AgcGain, + AgcShift, + FeLoopShift, + GammaAcq, + GammaRhoAcq, + GammaTrack, + GammaRhoTrack, + LockCountThreshold, + PhaseDiffThreshold; +}FE_DVBS2_CSMConfig_Params_t; + +typedef struct +{ + FE_DVBS2_RRCAlpha_t RRCAlpha; + FE_DVBS2_Mode_t ModeMode; + + S32 SymbolRate, + MasterClock, + CarrierFrequency, + AveFrameCoarse, + AveFramefine, + AgcThreshold; + + u16 SpectralInv; +} FE_STB0899_DVBS2_InitParams_t; + +typedef struct +{ + FE_DVBS2_AcqMode AcqMode; + /*FE_DVBS2_Mode_t mod;*/ + + u32 SymbolRate, + MasterClock, + FreqRange, + CenterFreq, + AveFrameCoarseAcq, + AveFramefineAcq, + AveFrameCoarseTrq, + AveFramefineTrq; + + S16 AutoReacq, + TracklockSel, + Zigzag, + StepSize; +}FE_DVBS2_ReacquireParams_t; + + +u32 FE_DVBS2_GetModCod(STCHIP_Handle_t hChip); + +S32 FE_DVBS2_GetUWPEsNo(STCHIP_Handle_t hChip, S32 Quant); + +u32 FE_DVBS2_GetSymbolRate(STCHIP_Handle_t hChip, u32 MasterClock); + +FE_DVBS2_State FE_DVBS2_GetState(STCHIP_Handle_t hChip, int Timeout); + +void FE_DVBS2_CSMInitialize(STCHIP_Handle_t hChip, int Pilots, FE_DVBS2_ModCod_t ModCode, u32 SymbolRate, u32 MasterClock); + +void FE_DVBS2_InitialCalculations(STCHIP_Handle_t hChip, FE_STB0899_DVBS2_InitParams_t *InitParams); + +void FE_DVBS2_Reacquire(STCHIP_Handle_t hChip, FE_DVBS2_ReacquireParams_t * ReacquireParams); + +long FE_DVBS2_CarrierWidth(long SymbolRate, FE_DVBS2_RRCAlpha_t Aplha); + + +#endif + + + diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/frontends/stb0899.h kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/stb0899.h --- kernel-2.6.24.4-orig/drivers/media/dvb/frontends/stb0899.h 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/stb0899.h 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,53 @@ +/* + * stb0899.c + * + * ST DVB-S2 Frontend Driver (stb0899) + * + * Copyright (C) 2001 fnbrd + * & 2002-2004 Andreas Oberritter + * & 2003 Wolfram Joost + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef STB0899_H +#define STB0899_H + +#include +#include "dvb_frontend.h" + + +struct stb0899_config +{ + u8 demod_address; + int (*fe_reset)(struct dvb_frontend *fe); +}; + + + +//#if defined(CONFIG_DVB_STB0899) || defined(CONFIG_DVB_STB0899_MODULE) +extern struct dvb_frontend* stb0899_attach(const struct stb0899_config* config,struct i2c_adapter* i2c); +/*#else +static inline struct dvb_frontend* stb0899_attach(const struct stb0899_config* config, + struct i2c_adapter* i2c) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __FUNCTION__); + return NULL; +} +#endif // CONFIG_DVB_STB0899_H*/ + +#endif // STB0899_H + diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/frontends/stb0899_init.c kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/stb0899_init.c --- kernel-2.6.24.4-orig/drivers/media/dvb/frontends/stb0899_init.c 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/stb0899_init.c 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,2682 @@ + + +#include "stb0899_init.h" + +STCHIP_Handle_t STB0899_Init(STB0899_InitParams_t *InitParams) +{ + STCHIP_Handle_t hChip = NULL; + u32 *DefVal; + + /* fill elements of external chip data structure */ + InitParams->Chip->NbRegs = STB0899_NBREGS; + InitParams->Chip->NbFields = STB0899_NBFIELDS; + InitParams->Chip->ChipMode = STCHIP_MODE_SUBADR_16; + + if(InitParams->NbDefVal == STB0899_NBREGS) + { + hChip = ChipOpen(InitParams->Chip); + DefVal = InitParams->DefVal; + + if(hChip != NULL) + { + /* ID */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_ID,"ID",0xf000,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_ID,FSTB0899_CHIP_IDENT,"CHIP_IDENT",4,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_ID,FSTB0899_RELEASE,"RELEASE",0,4,CHIP_UNSIGNED); + + /* TDISCNTRL1 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TDISCNTRL1,"TDISCNTRL1",0xf0a0,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TDISCNTRL1,FSTB0899_TIMOFF,"TIMOFF",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TDISCNTRL1,FSTB0899_DISEQC_RESET,"DISEQC_RESET",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TDISCNTRL1,FSTB0899_TIMCMD,"TIMCMD",4,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TDISCNTRL1,FSTB0899_TDISCNTRL1_RESERVED,"TDISCNTRL1_RESERVED",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TDISCNTRL1,FSTB0899_DISPRECHARGE,"DISPRECHARGE",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TDISCNTRL1,FSTB0899_DISEQCMODE,"DISEQCMODE",0,2,CHIP_UNSIGNED); + + /* DISCNTRL2 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DISCNTRL2,"DISCNTRL2",0xf0a1,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_DISCNTRL2,FSTB0899_RECEIVER_ON,"RECEIVER_ON",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DISCNTRL2,FSTB0899_IGNO_SHORT22K,"IGNO_SHORT22K",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DISCNTRL2,FSTB0899_ONECHIPTRX,"ONECHIPTRX",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DISCNTRL2,FSTB0899_EXTENVELOP,"EXTENVELOP",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DISCNTRL2,FSTB0899_PINSELECT,"PINSELECT",2,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DISCNTRL2,FSTB0899_IRQRXEND,"IRQRXEND",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DISCNTRL2,FSTB0899_IRQ4NBYTES,"IRQ4NBYTES",0,1,CHIP_UNSIGNED); + + /* DISRX_ST0 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DISRX_ST0,"DISRX_ST0",0xf0a4,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_DISRX_ST0,FSTB0899_RXEND,"RXEND",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DISRX_ST0,FSTB0899_RXACTIVE,"RXACTIVE",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DISRX_ST0,FSTB0899_SHORT22K,"SHORT22K",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DISRX_ST0,FSTB0899_CONTTONE,"CONTTONE",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DISRX_ST0,FSTB0899_DIS_4BFIFORDY,"DIS_4BFIFORDY",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DISRX_ST0,FSTB0899_FIFOEMPTY,"FIFOEMPTY",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DISRX_ST0,FSTB0899_DISRX_ST0_RESERVED,"DISRX_ST0_RESERVED",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DISRX_ST0,FSTB0899_ABORTRX,"ABORTRX",0,1,CHIP_UNSIGNED); + + /* DISRX_ST1 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DISRX_ST1,"DISRX_ST1",0xf0a5,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_DISRX_ST1,FSTB0899_RXFAIL,"RXFAIL",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DISRX_ST1,FSTB0899_FIFOPFAIL,"FIFOPFAIL",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DISRX_ST1,FSTB0899_RXNONBYTE,"RXNONBYTE",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DISRX_ST1,FSTB0899_FIFOOVF,"FIFOOVF",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DISRX_ST1,FSTB0899_FIFOBYTENBR,"FIFOBYTENBR",0,4,CHIP_UNSIGNED); + + /* DISPARITY */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DISPARITY,"DISPARITY",0xf0a6,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_DISPARITY,FSTB0899_DISEQC_PARITY,"DISEQC_PARITY",0,8,CHIP_UNSIGNED); + + /* DISFIFO */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DISFIFO,"DISFIFO",0xf0a7,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_DISFIFO,FSTB0899_DISEQCFIFO,"DISEQCFIFO",0,8,CHIP_UNSIGNED); + + /* DISSTATUS */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DISSTATUS,"DISSTATUS",0xf0a8,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_DISSTATUS,FSTB0899_TXFAIL,"TXFAIL",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DISSTATUS,FSTB0899_FIFOPARITYFAIL,"FIFOPARITYFAIL",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DISSTATUS,FSTB0899_DISS_RXNONBYTE,"DISS_RXNONBYTE",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DISSTATUS,FSTB0899_GAPBURST,"GAPBURST",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DISSTATUS,FSTB0899_TXFIFOBYTES,"TXFIFOBYTES",0,4,CHIP_UNSIGNED); + + /* DISF22 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DISF22,"DISF22",0xf0a9,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_DISF22,FSTB0899_F22,"F22",0,8,CHIP_UNSIGNED); + + /* DISF22RX */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DISF22RX,"DISF22RX",0xf0aa,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_DISF22RX,FSTB0899_F22RX,"F22RX",0,8,CHIP_UNSIGNED); + + /* SYSREG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_SYSREG,"SYSREG",0xf101,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_SYSREG,FSTB0899_SYS_MODE,"SYS_MODE",5,3,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_SYSREG,FSTB0899_DUPLMODE_IN,"DUPLMODE_IN",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_SYSREG,FSTB0899_DUPLIN_3CK,"DUPLIN_3CK",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_SYSREG,FSTB0899_DUPLMODE_OUT,"DUPLMODE_OUT",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_SYSREG,FSTB0899_SYSREG_1,"SYSREG_1",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_SYSREG,FSTB0899_RST_IQLSB_IN,"RST_IQLSB_IN",0,1,CHIP_UNSIGNED); + + /* ACRPRESC */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_ACRPRESC,"ACRPRESC",0xf110,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_ACRPRESC,FSTB0899_ACRPRESC_RESERVED,"ACRPRESC_RESERVED",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_ACRPRESC,FSTB0899_ACRPRESC,"ACRPRESC",4,3,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_ACRPRESC,FSTB0899_ACRPRESC_RESERVED2,"ACRPRESC_RESERVED2",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_ACRPRESC,FSTB0899_ACRPRESC2,"ACRPRESC2",0,3,CHIP_UNSIGNED); + + /* ACRDIV1 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_ACRDIV1,"ACRDIV1",0xf111,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_ACRDIV1,FSTB0899_ACRDIV1,"ACRDIV1",0,8,CHIP_UNSIGNED); + + /* ACRDIV2 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_ACRDIV2,"ACRDIV2",0xf112,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_ACRDIV2,FSTB0899_ACRDIV2,"ACRDIV2",0,8,CHIP_UNSIGNED); + + /* DACR1 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DACR1,"DACR1",0xf113,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_DACR1,FSTB0899_DACMODE,"DACMODE",5,3,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DACR1,FSTB0899_DACHZ,"DACHZ",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DACR1,FSTB0899_DAC_MSB,"DAC_MSB",0,4,CHIP_UNSIGNED); + + /* DACR2 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DACR2,"DACR2",0xf114,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_DACR2,FSTB0899_DAC_LSB,"DAC_LSB",0,8,CHIP_UNSIGNED); + + /* OUTCFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_OUTCFG,"OUTCFG",0xf11c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_OUTCFG,FSTB0899_TSSEROUTHZ,"TSSEROUTHZ",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_OUTCFG,FSTB0899_TSPOUTHZ,"TSPOUTHZ",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_OUTCFG,FSTB0899_OUTCFG_RESERVED,"OUTCFG_RESERVED",0,6,CHIP_UNSIGNED); + + /* MODECFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_MODECFG,"MODECFG",0xf11d,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_MODECFG,FSTB0899_INV_DATA,"INV_DATA",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_MODECFG,FSTB0899_INV_DATA6,"INV_DATA6",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_MODECFG,FSTB0899_MODECFG_RESERVED,"MODECFG_RESERVED",3,3,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_MODECFG,FSTB0899_INV_ERROR,"INV_ERROR",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_MODECFG,FSTB0899_INV_STROUT,"INV_STROUT",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_MODECFG,FSTB0899_INV_DP,"INV_DP",0,1,CHIP_UNSIGNED); + + /* IRQSTATUS3 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_IRQSTATUS3,"IRQSTATUS3",0xf120,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_IRQSTATUS3,FSTB0899_SIP1,"SIP1",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS3,FSTB0899_NSIP1,"NSIP1",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS3,FSTB0899_SCF_SYNC,"SCF_SYNC",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS3,FSTB0899_NSCF_SYNC,"NSCF_SYNC",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS3,FSTB0899_SAGC0_LOCK,"SAGC0_LOCK",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS3,FSTB0899_NSAGC0_LOCK,"NSAGC0_LOCK",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS3,FSTB0899_SDISEQCTX_IRQ,"SDISEQCTX_IRQ",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS3,FSTB0899_SDISEQCRX_IRQ,"SDISEQCRX_IRQ",0,1,CHIP_UNSIGNED); + + /* IRQSTATUS2 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_IRQSTATUS2,"IRQSTATUS2",0xf121,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_IRQSTATUS2,FSTB0899_SEND_LOOPTC,"SEND_LOOPTC",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS2,FSTB0899_SOV_RSFIFO,"SOV_RSFIFO",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS2,FSTB0899_SLOCKEDBW,"SLOCKEDBW",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS2,FSTB0899_NSLOCKEDBW,"NSLOCKEDBW",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS2,FSTB0899_SPRFBW,"SPRFBW",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS2,FSTB0899_NSPRFBW,"NSPRFBW",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS2,FSTB0899_SINPUTX,"SINPUTX",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS2,FSTB0899_NSINPUTX,"NSINPUTX",0,1,CHIP_UNSIGNED); + + /* IRQSTATUS1 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_IRQSTATUS1,"IRQSTATUS1",0xf122,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_IRQSTATUS1,FSTB0899_SEND_LOOPVIT,"SEND_LOOPVIT",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS1,FSTB0899_SDMON_ELOOP,"SDMON_ELOOP",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS1,FSTB0899_SLOCKED,"SLOCKED",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS1,FSTB0899_NSLOCKED,"NSLOCKED",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS1,FSTB0899_SPRF,"SPRF",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS1,FSTB0899_NSPRF,"NSPRF",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS1,FSTB0899_SSMOTIF_LOCKED,"SSMOTIF_LOCKED",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS1,FSTB0899_NSSMOTIF_LOCD,"NSSMOTIF_LOCD",0,1,CHIP_UNSIGNED); + + /* IRQSTATUS0 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_IRQSTATUS0,"IRQSTATUS0",0xf123,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_IRQSTATUS0,FSTB0899_SFIFOFULL_CODIN,"SFIFOFULL_CODIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS0,FSTB0899_SCOD_NEAR_EMPTY,"SCOD_NEAR_EMPTY",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS0,FSTB0899_SCOD_FIFO_READY,"SCOD_FIFO_READY",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS0,FSTB0899_SDECIN_OVER,"SDECIN_OVER",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS0,FSTB0899_SRSSYNC_OK,"SRSSYNC_OK",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS0,FSTB0899_SLNBTX_IRQ,"SLNBTX_IRQ",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS0,FSTB0899_SSPY_ENDSIM,"SSPY_ENDSIM",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQSTATUS0,FSTB0899_SSPY_VALIDSI,"SSPY_VALIDSI",0,1,CHIP_UNSIGNED); + + /* IRQMSK3 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_IRQMSK3,"IRQMSK3",0xf124,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_IRQMSK3,FSTB0899_MIP1,"MIP1",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK3,FSTB0899_NMIP1,"NMIP1",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK3,FSTB0899_MCF_SYNC,"MCF_SYNC",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK3,FSTB0899_NMCF_SYNC,"NMCF_SYNC",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK3,FSTB0899_MAGC0_LOCK,"MAGC0_LOCK",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK3,FSTB0899_NMAGC0_LOCK,"NMAGC0_LOCK",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK3,FSTB0899_MDISEQCTX_IRQ,"MDISEQCTX_IRQ",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK3,FSTB0899_MDISEQCRX_IRQ,"MDISEQCRX_IRQ",0,1,CHIP_UNSIGNED); + + /* IRQMSK2 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_IRQMSK2,"IRQMSK2",0xf125,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_IRQMSK2,FSTB0899_MEND_LOOPTC,"MEND_LOOPTC",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK2,FSTB0899_MOV_RSFIFO,"MOV_RSFIFO",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK2,FSTB0899_MLOCKEDBW,"MLOCKEDBW",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK2,FSTB0899_NMLOCKEDBW,"NMLOCKEDBW",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK2,FSTB0899_MPRFBW,"MPRFBW",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK2,FSTB0899_NMPRFBW,"NMPRFBW",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK2,FSTB0899_MINPUTX,"MINPUTX",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK2,FSTB0899_NMINPUTX,"NMINPUTX",0,1,CHIP_UNSIGNED); + + /* IRQMSK1 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_IRQMSK1,"IRQMSK1",0xf126,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_IRQMSK1,FSTB0899_MEND_LOOPVIT,"MEND_LOOPVIT",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK1,FSTB0899_MDMON_ELOOP,"MDMON_ELOOP",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK1,FSTB0899_MLOCKED,"MLOCKED",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK1,FSTB0899_NMLOCKED,"NMLOCKED",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK1,FSTB0899_MPRF,"MPRF",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK1,FSTB0899_NMPRF,"NMPRF",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK1,FSTB0899_MSMOTIF_LOCKED,"MSMOTIF_LOCKED",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK1,FSTB0899_NMSMOTIF_LOCD,"NMSMOTIF_LOCD",0,1,CHIP_UNSIGNED); + + /* IRQMSK0 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_IRQMSK0,"IRQMSK0",0xf127,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_IRQMSK0,FSTB0899_NFIFOFULL_CODIN,"NFIFOFULL_CODIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK0,FSTB0899_NCOD_NEAR_EMPTY,"NCOD_NEAR_EMPTY",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK0,FSTB0899_MCOD_FIFO_READY,"MCOD_FIFO_READY",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK0,FSTB0899_MDECIN_OVER,"MDECIN_OVER",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK0,FSTB0899_MRSSYNC_OK,"MRSSYNC_OK",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK0,FSTB0899_MLNBTX_IRQ,"MLNBTX_IRQ",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK0,FSTB0899_MSPY_ENDSIM,"MSPY_ENDSIM",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQMSK0,FSTB0899_MSPY_VALIDSI,"MSPY_VALIDSI",0,1,CHIP_UNSIGNED); + + /* IRQCFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_IRQCFG,"IRQCFG",0xf128,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_IRQCFG,FSTB0899_NINV_IRQ17,"NINV_IRQ17",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQCFG,FSTB0899_SEL_IRQ17,"SEL_IRQ17",4,3,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQCFG,FSTB0899_INV_IRQ16,"INV_IRQ16",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IRQCFG,FSTB0899_SEL_IRQ16,"SEL_IRQ16",0,3,CHIP_UNSIGNED); + + /* I2CCFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_I2CCFG,"I2CCFG",0xf129,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_I2CCFG,FSTB0899_I2CCFG_RESERVED,"I2CCFG_RESERVED",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_I2CCFG,FSTB0899_I2CCFG_RESERVED2,"I2CCFG_RESERVED2",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_I2CCFG,FSTB0899_I2CCFG_RESERVED3,"I2CCFG_RESERVED3",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_I2CCFG,FSTB0899_I2CCFG_RESERVED4,"I2CCFG_RESERVED4",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_I2CCFG,FSTB0899_I2CFASTMODE,"I2CFASTMODE",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_I2CCFG,FSTB0899_STATUSWR,"STATUSWR",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_I2CCFG,FSTB0899_I2CADDRINC,"I2CADDRINC",0,2,CHIP_UNSIGNED); + + /* I2CRPT */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_I2CRPT,"I2CRPT",0xf12a,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_I2CRPT,FSTB0899_I2CTON,"I2CTON",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_I2CRPT,FSTB0899_ENARPTLEVEL,"ENARPTLEVEL",4,3,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_I2CRPT,FSTB0899_SCLTDELAY,"SCLTDELAY",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_I2CRPT,FSTB0899_STOPENA,"STOPENA",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_I2CRPT,FSTB0899_STOPSDAT2SDA,"STOPSDAT2SDA",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_I2CRPT,FSTB0899_I2CRPT_RESERVED,"I2CRPT_RESERVED",0,1,CHIP_UNSIGNED); + + /* IOPVALUE8 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_IOPVALUE8,"IOPVALUE8",0xf136,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_IOPVALUE8,FSTB0899_VTIME_COHERENT,"VTIME_COHERENT",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE8,FSTB0899_IOPVALUE8_6,"IOPVALUE8_6",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE8,FSTB0899_IOPVALUE8_5,"IOPVALUE8_5",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE8,FSTB0899_VIOP37,"VIOP37",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE8,FSTB0899_VIOP36,"VIOP36",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE8,FSTB0899_VIOP35,"VIOP35",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE8,FSTB0899_VIOP34,"VIOP34",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE8,FSTB0899_VIOP33,"VIOP33",0,1,CHIP_UNSIGNED); + + /* IOPVALUE7 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_IOPVALUE7,"IOPVALUE7",0xf137,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_IOPVALUE7,FSTB0899_VIOP32,"VIOP32",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE7,FSTB0899_VIOP31,"VIOP31",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE7,FSTB0899_VIOP30,"VIOP30",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE7,FSTB0899_VIOP27,"VIOP27",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE7,FSTB0899_VIOP26,"VIOP26",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE7,FSTB0899_VIOP25,"VIOP25",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE7,FSTB0899_VIOP24,"VIOP24",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE7,FSTB0899_VIOP23,"VIOP23",0,1,CHIP_UNSIGNED); + + /* IOPVALUE6 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_IOPVALUE6,"IOPVALUE6",0xf138,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_IOPVALUE6,FSTB0899_VIOP22,"VIOP22",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE6,FSTB0899_VIOP21,"VIOP21",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE6,FSTB0899_VIOP20,"VIOP20",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE6,FSTB0899_VIOP17,"VIOP17",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE6,FSTB0899_VIOP16,"VIOP16",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE6,FSTB0899_VIOP15,"VIOP15",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE6,FSTB0899_VIOP14,"VIOP14",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE6,FSTB0899_VIOP13,"VIOP13",0,1,CHIP_UNSIGNED); + + /* IOPVALUE5 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_IOPVALUE5,"IOPVALUE5",0xf139,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_IOPVALUE5,FSTB0899_VIOP12,"VIOP12",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE5,FSTB0899_VIOP11,"VIOP11",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE5,FSTB0899_VIOP10,"VIOP10",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE5,FSTB0899_VPACKDP,"VPACKDP",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE5,FSTB0899_VDEC_DATA6,"VDEC_DATA6",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE5,FSTB0899_VDEC_DATA5,"VDEC_DATA5",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE5,FSTB0899_VDEC_DATA4,"VDEC_DATA4",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE5,FSTB0899_VDEC_DATA3,"VDEC_DATA3",0,1,CHIP_UNSIGNED); + + /* IOPVALUE4 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_IOPVALUE4,"IOPVALUE4",0xf13a,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_IOPVALUE4,FSTB0899_VDEC_DATA2,"VDEC_DATA2",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE4,FSTB0899_VDEC_DATA1,"VDEC_DATA1",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE4,FSTB0899_VDEC_DATA0,"VDEC_DATA0",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE4,FSTB0899_VDISEQC_IN,"VDISEQC_IN",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE4,FSTB0899_VIP2,"VIP2",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE4,FSTB0899_VIP1_4,"VIP1_4",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE4,FSTB0899_VPACKSYNC_4,"VPACKSYNC_4",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE4,FSTB0899_VSDAT,"VSDAT",0,1,CHIP_UNSIGNED); + + /* IOPVALUE3 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_IOPVALUE3,"IOPVALUE3",0xf13b,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_IOPVALUE3,FSTB0899_VIOP5_3,"VIOP5_3",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE3,FSTB0899_VIOP4,"VIOP4",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE3,FSTB0899_VSCLT,"VSCLT",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE3,FSTB0899_VAGCRF,"VAGCRF",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE3,FSTB0899_VAGCQ,"VAGCQ",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE3,FSTB0899_VAGCIQ,"VAGCIQ",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE3,FSTB0899_VSDA,"VSDA",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE3,FSTB0899_VOP2,"VOP2",0,1,CHIP_UNSIGNED); + + /* IOPVALUE2 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_IOPVALUE2,"IOPVALUE2",0xf13c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_IOPVALUE2,FSTB0899_VOP1,"VOP1",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE2,FSTB0899_VOP0,"VOP0",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE2,FSTB0899_VERR_FLAG,"VERR_FLAG",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE2,FSTB0899_VSYNC_CLK,"VSYNC_CLK",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE2,FSTB0899_VPACK_CLK,"VPACK_CLK",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE2,FSTB0899_VDEC_DATA7,"VDEC_DATA7",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE2,FSTB0899_IOP4,"IOP4",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE2,FSTB0899_BYTE_CLK,"BYTE_CLK",0,1,CHIP_UNSIGNED); + + /* IOPVALUE1 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_IOPVALUE1,"IOPVALUE1",0xf13d,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_IOPVALUE1,FSTB0899_VDISEQC,"VDISEQC",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE1,FSTB0899_VSCL,"VSCL",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE1,FSTB0899_VAUX_CK,"VAUX_CK",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE1,FSTB0899_VDAC,"VDAC",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE1,FSTB0899_VIP1_1,"VIP1_1",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE1,FSTB0899_VIOP5_1,"VIOP5_1",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE1,FSTB0899_VATT,"VATT",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE1,FSTB0899_VT7_CS0,"VT7_CS0",0,1,CHIP_UNSIGNED); + + /* IOPVALUE0 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_IOPVALUE0,"IOPVALUE0",0xf13e,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_IOPVALUE0,FSTB0899_VT12_CS1,"VT12_CS1",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE0,FSTB0899_VT6_DIRCLK,"VT6_DIRCLK",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE0,FSTB0899_VENAFIFOI,"VENAFIFOI",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE0,FSTB0899_VPACKSYNC_0,"VPACKSYNC_0",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE0,FSTB0899_VDATACK,"VDATACK",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE0,FSTB0899_VDATA7,"VDATA7",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE0,FSTB0899_VT1_STDBY,"VT1_STDBY",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IOPVALUE0,FSTB0899_VIP0,"VIP0",0,1,CHIP_UNSIGNED); + + /* GPIO0CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO0CFG,"GPIO0CFG",0xf140,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO0CFG,FSTB0899_GPIO0_OPDRAIN,"GPIO0_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO0CFG,FSTB0899_GPIO0_CONFIG,"GPIO0_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO0CFG,FSTB0899_GPIO0_XOR,"GPIO0_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO1CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO1CFG,"GPIO1CFG",0xf141,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO1CFG,FSTB0899_GPIO1_OPDRAIN,"GPIO1_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO1CFG,FSTB0899_GPIO1_CONFIG,"GPIO1_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO1CFG,FSTB0899_GPIO1_XOR,"GPIO1_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO2CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO2CFG,"GPIO2CFG",0xf142,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO2CFG,FSTB0899_GPIO2_OPDRAIN,"GPIO2_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO2CFG,FSTB0899_GPIO2_CONFIG,"GPIO2_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO2CFG,FSTB0899_GPIO2_XOR,"GPIO2_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO3CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO3CFG,"GPIO3CFG",0xf143,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO3CFG,FSTB0899_GPIO3_OPDRAIN,"GPIO3_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO3CFG,FSTB0899_GPIO3_CONFIG,"GPIO3_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO3CFG,FSTB0899_GPIO3_XOR,"GPIO3_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO4CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO4CFG,"GPIO4CFG",0xf144,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO4CFG,FSTB0899_GPIO4_OPDRAIN,"GPIO4_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO4CFG,FSTB0899_GPIO4_CONFIG,"GPIO4_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO4CFG,FSTB0899_GPIO4_XOR,"GPIO4_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO5CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO5CFG,"GPIO5CFG",0xf145,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO5CFG,FSTB0899_GPIO5_OPDRAIN,"GPIO5_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO5CFG,FSTB0899_GPIO5_CONFIG,"GPIO5_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO5CFG,FSTB0899_GPIO5_XOR,"GPIO5_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO6CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO6CFG,"GPIO6CFG",0xf146,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO6CFG,FSTB0899_GPIO6_OPDRAIN,"GPIO6_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO6CFG,FSTB0899_GPIO6_CONFIG,"GPIO6_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO6CFG,FSTB0899_GPIO6_XOR,"GPIO6_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO7CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO7CFG,"GPIO7CFG",0xf147,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO7CFG,FSTB0899_GPIO7_OPDRAIN,"GPIO7_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO7CFG,FSTB0899_GPIO7_CONFIG,"GPIO7_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO7CFG,FSTB0899_GPIO7_XOR,"GPIO7_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO8CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO8CFG,"GPIO8CFG",0xf148,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO8CFG,FSTB0899_GPIO8_OPDRAIN,"GPIO8_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO8CFG,FSTB0899_GPIO8_CONFIG,"GPIO8_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO8CFG,FSTB0899_GPIO8_XOR,"GPIO8_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO9CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO9CFG,"GPIO9CFG",0xf149,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO9CFG,FSTB0899_GPIO9_OPDRAIN,"GPIO9_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO9CFG,FSTB0899_GPIO9_CONFIG,"GPIO9_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO9CFG,FSTB0899_GPIO9_XOR,"GPIO9_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO10CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO10CFG,"GPIO10CFG",0xf14a,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO10CFG,FSTB0899_GPIO10_OPDRAIN,"GPIO10_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO10CFG,FSTB0899_GPIO10_CONFIG,"GPIO10_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO10CFG,FSTB0899_GPIO10_XOR,"GPIO10_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO11CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO11CFG,"GPIO11CFG",0xf14b,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO11CFG,FSTB0899_GPIO11_OPDRAIN,"GPIO11_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO11CFG,FSTB0899_GPIO11_CONFIG,"GPIO11_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO11CFG,FSTB0899_GPIO11_XOR,"GPIO11_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO12CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO12CFG,"GPIO12CFG",0xf14c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO12CFG,FSTB0899_GPIO12_OPDRAIN,"GPIO12_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO12CFG,FSTB0899_GPIO12_CONFIG,"GPIO12_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO12CFG,FSTB0899_GPIO12_XOR,"GPIO12_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO13CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO13CFG,"GPIO13CFG",0xf14d,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO13CFG,FSTB0899_GPIO13_OPDRAIN,"GPIO13_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO13CFG,FSTB0899_GPIO13_CONFIG,"GPIO13_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO13CFG,FSTB0899_GPIO13_XOR,"GPIO13_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO14CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO14CFG,"GPIO14CFG",0xf14e,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO14CFG,FSTB0899_GPIO14_OPDRAIN,"GPIO14_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO14CFG,FSTB0899_GPIO14_CONFIG,"GPIO14_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO14CFG,FSTB0899_GPIO14_XOR,"GPIO14_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO15CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO15CFG,"GPIO15CFG",0xf14f,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO15CFG,FSTB0899_GPIO15_OPDRAIN,"GPIO15_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO15CFG,FSTB0899_GPIO15_CONFIG,"GPIO15_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO15CFG,FSTB0899_GPIO15_XOR,"GPIO15_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO16CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO16CFG,"GPIO16CFG",0xf150,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO16CFG,FSTB0899_GPIO16_OPDRAIN,"GPIO16_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO16CFG,FSTB0899_GPIO16_CONFIG,"GPIO16_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO16CFG,FSTB0899_GPIO16_XOR,"GPIO16_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO17CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO17CFG,"GPIO17CFG",0xf151,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO17CFG,FSTB0899_GPIO17_OPDRAIN,"GPIO17_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO17CFG,FSTB0899_GPIO17_CONFIG,"GPIO17_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO17CFG,FSTB0899_GPIO17_XOR,"GPIO17_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO18CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO18CFG,"GPIO18CFG",0xf152,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO18CFG,FSTB0899_GPIO18_OPDRAIN,"GPIO18_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO18CFG,FSTB0899_GPIO18_CONFIG,"GPIO18_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO18CFG,FSTB0899_GPIO18_XOR,"GPIO18_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO19CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO19CFG,"GPIO19CFG",0xf153,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO19CFG,FSTB0899_GPIO19_OPDRAIN,"GPIO19_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO19CFG,FSTB0899_GPIO19_CONFIG,"GPIO19_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO19CFG,FSTB0899_GPIO19_XOR,"GPIO19_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO20CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO20CFG,"GPIO20CFG",0xf154,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO20CFG,FSTB0899_GPIO20_OPDRAIN,"GPIO20_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO20CFG,FSTB0899_GPIO20_CONFIG,"GPIO20_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO20CFG,FSTB0899_GPIO20_XOR,"GPIO20_XOR",0,1,CHIP_UNSIGNED); + + /* SDATCFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_SDATCFG,"SDATCFG",0xf155,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_SDATCFG,FSTB0899_SDAT_OPDRAIN,"SDAT_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_SDATCFG,FSTB0899_SDAT_CONFIG,"SDAT_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_SDATCFG,FSTB0899_SDAT_XOR,"SDAT_XOR",0,1,CHIP_UNSIGNED); + + /* SCLTCFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_SCLTCFG,"SCLTCFG",0xf156,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_SCLTCFG,FSTB0899_SCLT_OPDRAIN,"SCLT_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_SCLTCFG,FSTB0899_SCLT_CONFIG,"SCLT_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_SCLTCFG,FSTB0899_SCLT_XOR,"SCLT_XOR",0,1,CHIP_UNSIGNED); + + /* AGCRFCFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_AGCRFCFG,"AGCRFCFG",0xf157,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_AGCRFCFG,FSTB0899_AGCRF_OPDRAIN,"AGCRF_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_AGCRFCFG,FSTB0899_AGCRF_CONFIG,"AGCRF_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_AGCRFCFG,FSTB0899_AGCRF_XOR,"AGCRF_XOR",0,1,CHIP_UNSIGNED); + + /* AGCBB2CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_AGCBB2CFG,"AGCBB2CFG",0xf158,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_AGCBB2CFG,FSTB0899_AGCBB2_OPDRAIN,"AGCBB2_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_AGCBB2CFG,FSTB0899_AGCBB2_CONFIG,"AGCBB2_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_AGCBB2CFG,FSTB0899_AGCBB2_XOR,"AGCBB2_XOR",0,1,CHIP_UNSIGNED); + + /* AGCBB1CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_AGCBB1CFG,"AGCBB1CFG",0xf159,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_AGCBB1CFG,FSTB0899_AGCBB1_OPDRAIN,"AGCBB1_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_AGCBB1CFG,FSTB0899_AGCBB1_CONFIG,"AGCBB1_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_AGCBB1CFG,FSTB0899_AGCBB1_XOR,"AGCBB1_XOR",0,1,CHIP_UNSIGNED); + + /* DIRCLKCFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DIRCLKCFG,"DIRCLKCFG",0xf15a,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_DIRCLKCFG,FSTB0899_DIRCLK_OPDRAIN,"DIRCLK_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DIRCLKCFG,FSTB0899_DIRCLK_CONFIG,"DIRCLK_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DIRCLKCFG,FSTB0899_DIRCLK_XOR,"DIRCLK_XOR",0,1,CHIP_UNSIGNED); + + /* CKOUT27CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_CKOUT27CFG,"CKOUT27CFG",0xf15b,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_CKOUT27CFG,FSTB0899_CKOUT27_OPDRAIN,"CKOUT27_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CKOUT27CFG,FSTB0899_CKOUT27_CONFIG,"CKOUT27_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CKOUT27CFG,FSTB0899_CKOUT27_XOR,"CKOUT27_XOR",0,1,CHIP_UNSIGNED); + + /* STDBYCFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_STDBYCFG,"STDBYCFG",0xf15c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_STDBYCFG,FSTB0899_STDBY_OPDRAIN,"STDBY_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_STDBYCFG,FSTB0899_STDBY_CONFIG,"STDBY_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_STDBYCFG,FSTB0899_STDBY_XOR,"STDBY_XOR",0,1,CHIP_UNSIGNED); + + /* CS0CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_CS0CFG,"CS0CFG",0xf15d,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_CS0CFG,FSTB0899_CS0_OPDRAIN,"CS0_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CS0CFG,FSTB0899_CS0_CONFIG,"CS0_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CS0CFG,FSTB0899_CS0_XOR,"CS0_XOR",0,1,CHIP_UNSIGNED); + + /* CS1CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_CS1CFG,"CS1CFG",0xf15e,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_CS1CFG,FSTB0899_CS1_OPDRAIN,"CS1_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CS1CFG,FSTB0899_CS1_CONFIG,"CS1_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CS1CFG,FSTB0899_CS1_XOR,"CS1_XOR",0,1,CHIP_UNSIGNED); + + /* DISEQCOCFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DISEQCOCFG,"DISEQCOCFG",0xf15f,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_DISEQCOCFG,FSTB0899_DISEQCO_OPDRAIN,"DISEQCO_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DISEQCOCFG,FSTB0899_DISEQCO_CONFIG,"DISEQCO_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DISEQCOCFG,FSTB0899_DISEQCO_XOR,"DISEQCO_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO32CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO32CFG,"GPIO32CFG",0xf160,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO32CFG,FSTB0899_GPIO32_OPDRAIN,"GPIO32_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO32CFG,FSTB0899_GPIO32_CONFIG,"GPIO32_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO32CFG,FSTB0899_GPIO32_XOR,"GPIO32_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO33CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO33CFG,"GPIO33CFG",0xf161,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO33CFG,FSTB0899_GPIO33_OPDRAIN,"GPIO33_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO33CFG,FSTB0899_GPIO33_CONFIG,"GPIO33_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO33CFG,FSTB0899_GPIO33_XOR,"GPIO33_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO34CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO34CFG,"GPIO34CFG",0xf162,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO34CFG,FSTB0899_GPIO34_OPDRAIN,"GPIO34_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO34CFG,FSTB0899_GPIO34_CONFIG,"GPIO34_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO34CFG,FSTB0899_GPIO34_XOR,"GPIO34_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO35CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO35CFG,"GPIO35CFG",0xf163,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO35CFG,FSTB0899_GPIO35_OPDRAIN,"GPIO35_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO35CFG,FSTB0899_GPIO35_CONFIG,"GPIO35_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO35CFG,FSTB0899_GPIO35_XOR,"GPIO35_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO36CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO36CFG,"GPIO36CFG",0xf164,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO36CFG,FSTB0899_GPIO36_OPDRAIN,"GPIO36_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO36CFG,FSTB0899_GPIO36_CONFIG,"GPIO36_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO36CFG,FSTB0899_GPIO36_XOR,"GPIO36_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO37CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO37CFG,"GPIO37CFG",0xf165,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO37CFG,FSTB0899_GPIO37_OPDRAIN,"GPIO37_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO37CFG,FSTB0899_GPIO37_CONFIG,"GPIO37_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO37CFG,FSTB0899_GPIO37_XOR,"GPIO37_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO38CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO38CFG,"GPIO38CFG",0xf166,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO38CFG,FSTB0899_GPIO38_OPDRAIN,"GPIO38_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO38CFG,FSTB0899_GPIO38_CONFIG,"GPIO38_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO38CFG,FSTB0899_GPIO38_XOR,"GPIO38_XOR",0,1,CHIP_UNSIGNED); + + /* GPIO39CFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GPIO39CFG,"GPIO39CFG",0xf167,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GPIO39CFG,FSTB0899_GPIO39_OPDRAIN,"GPIO39_OPDRAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO39CFG,FSTB0899_GPIO39_CONFIG,"GPIO39_CONFIG",1,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_GPIO39CFG,FSTB0899_GPIO39_XOR,"GPIO39_XOR",0,1,CHIP_UNSIGNED); + + /* NCOARSE */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_NCOARSE,"NCOARSE",0xf1b3,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_NCOARSE,FSTB0899_MDIV,"MDIV",0,8,CHIP_UNSIGNED); + + /* SYNTCTRL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_SYNTCTRL,"SYNTCTRL",0xf1b6,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_SYNTCTRL,FSTB0899_STANDBY,"STANDBY",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_SYNTCTRL,FSTB0899_BYPASS_PLLCORE,"BYPASS_PLLCORE",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_SYNTCTRL,FSTB0899_SELX1RATIO,"SELX1RATIO",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_SYNTCTRL,FSTB0899_I2C_TUD,"I2C_TUD",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_SYNTCTRL,FSTB0899_STOP_PLL,"STOP_PLL",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_SYNTCTRL,FSTB0899_SYNTCTRL_RESERVED,"SYNTCTRL_RESERVED",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_SYNTCTRL,FSTB0899_SELOSCI,"SELOSCI",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_SYNTCTRL,FSTB0899_BYPASSPLLADC,"BYPASSPLLADC",0,1,CHIP_UNSIGNED); + + /* FILTCTRL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_FILTCTRL,"FILTCTRL",0xf1b7,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_FILTCTRL,FSTB0899_INVCLK90,"INVCLK90",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_FILTCTRL,FSTB0899_PERMBYPDIS,"PERMBYPDIS",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_FILTCTRL,FSTB0899_CLKSWITCH,"CLKSWITCH",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_FILTCTRL,FSTB0899_FILTCTRL_RESERVED,"FILTCTRL_RESERVED",0,5,CHIP_UNSIGNED); + + /* SYSCTRL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_SYSCTRL,"SYSCTRL",0xf1b8,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_SYSCTRL,FSTB0899_SYSCTRL_RESERVED,"SYSCTRL_RESERVED",1,7,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_SYSCTRL,FSTB0899_PLLLOCKED,"PLLLOCKED",0,1,CHIP_UNSIGNED); + + /* STOPCLK1 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_STOPCLK1,"STOPCLK1",0xf1c2,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_STOPCLK1,FSTB0899_STOP_CKINTBUF90,"STOP_CKINTBUF90",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_STOPCLK1,FSTB0899_STOP_CKINTBUF180,"STOP_CKINTBUF180",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_STOPCLK1,FSTB0899_STOP_CKH8PSK90,"STOP_CKH8PSK90",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_STOPCLK1,FSTB0899_STOP_CKFEC90,"STOP_CKFEC90",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_STOPCLK1,FSTB0899_STOP_CKFEC180,"STOP_CKFEC180",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_STOPCLK1,FSTB0899_STOP_CKCORE270,"STOP_CKCORE270",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_STOPCLK1,FSTB0899_STOP_CKADCI90,"STOP_CKADCI90",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_STOPCLK1,FSTB0899_STOP_INVCKADCI90,"STOP_INVCKADCI90",0,1,CHIP_UNSIGNED); + + /* STOPCLK2 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_STOPCLK2,"STOPCLK2",0xf1c3,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_STOPCLK2,FSTB0899_STOPCLK2_RESERVED,"STOPCLK2_RESERVED",3,5,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_STOPCLK2,FSTB0899_STOP_CKS2DMD90,"STOP_CKS2DMD90",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_STOPCLK2,FSTB0899_STOP_CKPKDLIN90,"STOP_CKPKDLIN90",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_STOPCLK2,FSTB0899_STOP_CKPKDLIN180,"STOP_CKPKDLIN180",0,1,CHIP_UNSIGNED); + + /* TSTTNR1 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTTNR1,"TSTTNR1",0xf1e0,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTTNR1,FSTB0899_BYPASS_ADC,"BYPASS_ADC",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTTNR1,FSTB0899_INVADCICKOUT,"INVADCICKOUT",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTTNR1,FSTB0899_ADCTEST_VOLTAGE,"ADCTEST_VOLTAGE",4,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTTNR1,FSTB0899_ADC_RESET,"ADC_RESET",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTTNR1,FSTB0899_TSTTNR1_2,"TSTTNR1_2",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTTNR1,FSTB0899_ADCPON,"ADCPON",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTTNR1,FSTB0899_ADCIN_MODE,"ADCIN_MODE",0,1,CHIP_UNSIGNED); + + /* TSTTNR2 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTTNR2,"TSTTNR2",0xf1e1,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTTNR2,FSTB0899_TSTTNR2_7,"TSTTNR2_7",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTTNR2,FSTB0899_NOT_DISRX_WIRED,"NOT_DISRX_WIRED",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTTNR2,FSTB0899_DISEQC_DCURRENT,"DISEQC_DCURRENT",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTTNR2,FSTB0899_DISEQC_ZCURRENT,"DISEQC_ZCURRENT",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTTNR2,FSTB0899_DISEQC_SINC_SOURCE,"DISEQC_SINC_SOURCE",2,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTTNR2,FSTB0899_SELIQSRC,"SELIQSRC",0,2,CHIP_UNSIGNED); + + /* TSTTNR3 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTTNR3,"TSTTNR3",0xf1e2,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTTNR3,FSTB0899_TSTTNR3_7,"TSTTNR3_7",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTTNR3,FSTB0899_TSTTNR3_6,"TSTTNR3_6",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTTNR3,FSTB0899_TSTTNR3_5,"TSTTNR3_5",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTTNR3,FSTB0899_TSTTNR3_4,"TSTTNR3_4",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTTNR3,FSTB0899_TSTTNR3_3,"TSTTNR3_3",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTTNR3,FSTB0899_TSTTNR3_2,"TSTTNR3_2",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTTNR3,FSTB0899_TSTTNR3_1,"TSTTNR3_1",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTTNR3,FSTB0899_TSTTNR3_0,"TSTTNR3_0",0,1,CHIP_UNSIGNED); + + /* INTBUFSTATUS */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_INTBUFSTATUS,"INTBUFSTATUS",0xf200,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_INTBUFSTATUS,FSTB0899_INTBUF_FIFO_FULL,"INTBUF_FIFO_FULL",0,1,CHIP_UNSIGNED); + + /* INTBUFCTRL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_INTBUFCTRL,"INTBUFCTRL",0xf201,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_INTBUFCTRL,FSTB0899_H8S2_PATH_DECODE,"H8S2_PATH_DECODE",2,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_INTBUFCTRL,FSTB0899_FIFO_ENABLE,"FIFO_ENABLE",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_INTBUFCTRL,FSTB0899_INTBUF_SOFTRESET,"INTBUF_SOFTRESET",0,1,CHIP_UNSIGNED); + + /* DMDSTATUS */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_DMDSTATUS,"DMDSTATUS",0xf300,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_DMDSTATUS,FSTB0899_IF_AGCLOCK,"IF_AGCLOCK",8,1,CHIP_UNSIGNED); + + /* CRLFREQ */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_CRLFREQ,"CRLFREQ",0xf304,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_CRLFREQ,FSTB0899_CRL_FREQUENCY,"CRL_FREQUENCY",0,30,CHIP_SIGNED); + + /* BTRFREQ */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_BTRFREQ,"BTRFREQ",0xf308,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_BTRFREQ,FSTB0899_BTR_FREQUENCY,"BTR_FREQUENCY",0,28,CHIP_SIGNED); + + /* IFAGCGAIN */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_IFAGCGAIN,"IFAGCGAIN",0xf30c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_IFAGCGAIN,FSTB0899_IF_AGCGAIN,"IF_AGCGAIN",0,14,CHIP_UNSIGNED); + + /* BBAGCGAIN */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_BBAGCGAIN,"BBAGCGAIN",0xf310,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_BBAGCGAIN,FSTB0899_BB_AGCGAIN,"BB_AGCGAIN",0,14,CHIP_UNSIGNED); + + /* DCOFFSET */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_DCOFFSET,"DCOFFSET",0xf314,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_DCOFFSET,FSTB0899_I_DCOFFSET,"I_DCOFFSET",8,8,CHIP_SIGNED); + ChipAddField(hChip,RSTB0899_DCOFFSET,FSTB0899_Q_DCOFFSET,"Q_DCOFFSET",0,8,CHIP_SIGNED); + + /* DMDCNTRL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DMDCNTRL,"DMDCNTRL",0xf31c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_DMDCNTRL,FSTB0899_ADC0_PINS1IN,"ADC0_PINS1IN",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DMDCNTRL,FSTB0899_IN2COMP1_OFFBIN0,"IN2COMP1_OFFBIN0",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DMDCNTRL,FSTB0899_DC_COMP,"DC_COMP",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DMDCNTRL,FSTB0899_MODMODE,"MODMODE",0,2,CHIP_UNSIGNED); + + /* IFAGCCNTRL */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_IFAGCCNTRL,"IFAGCCNTRL",0xf320,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_IFAGCCNTRL,FSTB0899_IF_GAININIT,"IF_GAININIT",13,14,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IFAGCCNTRL,FSTB0899_IF_AGCSENSE,"IF_AGCSENSE",12,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IFAGCCNTRL,FSTB0899_IF_LOOPGAIN,"IF_LOOPGAIN",8,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IFAGCCNTRL,FSTB0899_IF_LDGAININIT,"IF_LDGAININIT",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IFAGCCNTRL,FSTB0899_IF_AGCREF,"IF_AGCREF",0,7,CHIP_UNSIGNED); + + /* BBAGCCNTRL */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_BBAGCCNTRL,"BBAGCCNTRL",0xf324,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_BBAGCCNTRL,FSTB0899_BBGAIN_INIT,"BBGAIN_INIT",12,14,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BBAGCCNTRL,FSTB0899_BBLOOP_GAIN,"BBLOOP_GAIN",8,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BBAGCCNTRL,FSTB0899_BBLDGAIN_INIT,"BBLDGAIN_INIT",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BBAGCCNTRL,FSTB0899_BB_AGCREF,"BB_AGCREF",0,7,CHIP_UNSIGNED); + + /* CRLCNTRL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_CRLCNTRL,"CRLCNTRL",0xf328,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_CRLCNTRL,FSTB0899_CRL_LOCK_CLEAR,"CRL_LOCK_CLEAR",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CRLCNTRL,FSTB0899_CRL_CLR_SWEEPER,"CRL_CLR_SWEEPER",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CRLCNTRL,FSTB0899_CRL_SWEEP_EN,"CRL_SWEEP_EN",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CRLCNTRL,FSTB0899_CRL_DETECTOR_SEL,"CRL_DETECTOR_SEL",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CRLCNTRL,FSTB0899_CRL_SENSE,"CRL_SENSE",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CRLCNTRL,FSTB0899_CRL_CLR_PHSERR,"CRL_CLR_PHSERR",0,1,CHIP_UNSIGNED); + + /* CRLPHSINIT */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_CRLPHSINIT,"CRLPHSINIT",0xf32c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_CRLPHSINIT,FSTB0899_CRLPHSINIT31,"CRLPHSINIT31",30,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CRLPHSINIT,FSTB0899_CRL_LD_INIT_PHASE,"CRL_LD_INIT_PHASE",24,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CRLPHSINIT,FSTB0899_CRL_INIT_PHASE,"CRL_INIT_PHASE",0,24,CHIP_UNSIGNED); + + /* CRLFREQINIT */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_CRLFREQINIT,"CRLFREQINIT",0xf330,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_CRLFREQINIT,FSTB0899_CRLFREQINIT31,"CRLFREQINIT31",30,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CRLFREQINIT,FSTB0899_CRL_LD_FREQ_INIT,"CRL_LD_FREQ_INIT",24,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CRLFREQINIT,FSTB0899_CRL_FREQ_INIT,"CRL_FREQ_INIT",0,24,CHIP_UNSIGNED); + + /* CRLLOOPGAIN */ + ChipAddReg(hChip,STCHIP_REG_24,RSTB0899_CRLLOOPGAIN,"CRLLOOPGAIN",0xf334,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_CRLLOOPGAIN,FSTB0899_KCRL2_RSHFT,"KCRL2_RSHFT",16,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CRLLOOPGAIN,FSTB0899_KCRL1,"KCRL1",12,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CRLLOOPGAIN,FSTB0899_KCRL1_RSHFT,"KCRL1_RSHFT",8,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CRLLOOPGAIN,FSTB0899_KCRL0,"KCRL0",4,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CRLLOOPGAIN,FSTB0899_KCRL0_RSHFT,"KCRL0_RSHFT",0,4,CHIP_UNSIGNED); + + /* CRLNOMFREQ */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_CRLNOMFREQ,"CRLNOMFREQ",0xf338,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_CRLNOMFREQ,FSTB0899_CRLNOM_FREQ,"CRLNOM_FREQ",0,30,CHIP_UNSIGNED); + + /* CRLSWPRATE */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_CRLSWPRATE,"CRLSWPRATE",0xf33c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_CRLSWPRATE,FSTB0899_CRL_SWP_RATE,"CRL_SWP_RATE",0,30,CHIP_UNSIGNED); + + /* CRLMAXSWP */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_CRLMAXSWP,"CRLMAXSWP",0xf340,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_CRLMAXSWP,FSTB0899_CRL_MAX_SWP,"CRL_MAX_SWP",0,30,CHIP_UNSIGNED); + + /* CRLLKCNTRL */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_CRLLKCNTRL,"CRLLKCNTRL",0xf344,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_CRLLKCNTRL,FSTB0899_CRL_PWR_DET,"CRL_PWR_DET",24,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CRLLKCNTRL,FSTB0899_THRESHOLD_LI,"THRESHOLD_LI",16,8,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CRLLKCNTRL,FSTB0899_THRESHOLD_HI,"THRESHOLD_HI",8,8,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CRLLKCNTRL,FSTB0899_CRLK_GAIN,"CRLK_GAIN",6,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CRLLKCNTRL,FSTB0899_CRLK_FC,"CRLK_FC",0,6,CHIP_UNSIGNED); + + /* DECIMCNTRL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DECIMCNTRL,"DECIMCNTRL",0xf348,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_DECIMCNTRL,FSTB0899_BANDLIMIT_B,"BANDLIMIT_B",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DECIMCNTRL,FSTB0899_WIN_SEL,"WIN_SEL",3,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DECIMCNTRL,FSTB0899_DECIM_RATE,"DECIM_RATE",0,3,CHIP_UNSIGNED); + + /* BTRCNTRL */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_BTRCNTRL,"BTRCNTRL",0xf34c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_BTRCNTRL,FSTB0899_BTRFREQ_CORR,"BTRFREQ_CORR",4,11,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BTRCNTRL,FSTB0899_BTRCLR_LOCK,"BTRCLR_LOCK",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BTRCNTRL,FSTB0899_BTR_SENS,"BTR_SENS",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BTRCNTRL,FSTB0899_BTRERR_ENA,"BTRERR_ENA",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BTRCNTRL,FSTB0899_INTRP_PHS_SENS,"INTRP_PHS_SENS",0,1,CHIP_UNSIGNED); + + /* BTRLOOPGAIN */ + ChipAddReg(hChip,STCHIP_REG_24,RSTB0899_BTRLOOPGAIN,"BTRLOOPGAIN",0xf350,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_BTRLOOPGAIN,FSTB0899_KBTR2_RSHT,"KBTR2_RSHT",16,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BTRLOOPGAIN,FSTB0899_KBTR1,"KBTR1",12,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BTRLOOPGAIN,FSTB0899_KBTR1_RSHT,"KBTR1_RSHT",8,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BTRLOOPGAIN,FSTB0899_KBTR0,"KBTR0",4,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BTRLOOPGAIN,FSTB0899_KBTR0_RSHFT,"KBTR0_RSHFT",0,4,CHIP_UNSIGNED); + + /* BTRPHSINIT */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_BTRPHSINIT,"BTRPHSINIT",0xf354,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_BTRPHSINIT,FSTB0899_BTRID_PHASEINIT,"BTRID_PHASEINIT",28,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BTRPHSINIT,FSTB0899_BTR_INITPHASE,"BTR_INITPHASE",0,28,CHIP_UNSIGNED); + + /* BTRFREQINIT */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_BTRFREQINIT,"BTRFREQINIT",0xf358,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_BTRFREQINIT,FSTB0899_BTRID_FREQINIT,"BTRID_FREQINIT",28,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BTRFREQINIT,FSTB0899_BTR_FREQINIT,"BTR_FREQINIT",0,28,CHIP_UNSIGNED); + + /* BTRNOMFREQ */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_BTRNOMFREQ,"BTRNOMFREQ",0xf35c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_BTRNOMFREQ,FSTB0899_BTRNOM_FREQ,"BTRNOM_FREQ",0,28,CHIP_UNSIGNED); + + /* BTRLKCNTRL */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_BTRLKCNTRL,"BTRLKCNTRL",0xf360,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_BTRLKCNTRL,FSTB0899_BTR_MINENERGY,"BTR_MINENERGY",24,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BTRLKCNTRL,FSTB0899_BTR_LOCK_THRESHOLDLO,"BTR_LOCK_THRESHOLDLO",16,8,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BTRLKCNTRL,FSTB0899_BTR_LOCK_THRESHOLDHI,"BTR_LOCK_THRESHOLDHI",8,8,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BTRLKCNTRL,FSTB0899_BTR_LOCKGAIN,"BTR_LOCKGAIN",6,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BTRLKCNTRL,FSTB0899_BTR_LOCK_LEAKFACTOR,"BTR_LOCK_LEAKFACTOR",0,6,CHIP_UNSIGNED); + + /* DECNCNTRL */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_DECNCNTRL,"DECNCNTRL",0xf364,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_DECNCNTRL,FSTB0899_INVERT_Q,"INVERT_Q",8,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DECNCNTRL,FSTB0899_INVERT_I,"INVERT_I",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DECNCNTRL,FSTB0899_SWAP_IQ,"SWAP_IQ",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DECNCNTRL,FSTB0899_SOFT_THRESHOLD,"SOFT_THRESHOLD",0,6,CHIP_UNSIGNED); + + /* TPCNTRL */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPCNTRL,"TPCNTRL",0xf368,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_TPCNTRL,FSTB0899_TP_MSB1LSB0_SEL,"TP_MSB1LSB0_SEL",15,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TPCNTRL,FSTB0899_CAPTURE,"CAPTURE",14,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TPCNTRL,FSTB0899_TP_BLK_SEL,"TP_BLK_SEL",9,5,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TPCNTRL,FSTB0899_TP_SIG_SEL,"TP_SIG_SEL",4,5,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TPCNTRL,FSTB0899_TP_SEL,"TP_SEL",0,4,CHIP_UNSIGNED); + + /* TPBUFSTATUS */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TPBUFSTATUS,"TPBUFSTATUS",0xf36c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_TPBUFSTATUS,FSTB0899_BUFFER_FULL,"BUFFER_FULL",0,1,CHIP_UNSIGNED); + + /* DCESTIM */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_DCESTIM,"DCESTIM",0xf37c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x0); + ChipAddField(hChip,RSTB0899_DCESTIM,FSTB0899_I_DC_ESTIMATE,"I_DC_ESTIMATE",8,8,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DCESTIM,FSTB0899_Q_DC_ESTIMATE,"Q_DC_ESTIMATE",0,8,CHIP_UNSIGNED); + + /* FLLCNTRL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_FLLCNTRL,"FLLCNTRL",0xf310,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x20); + ChipAddField(hChip,RSTB0899_FLLCNTRL,FSTB0899_CRL_FLL_ACC,"CRL_FLL_ACC",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_FLLCNTRL,FSTB0899_FLL_AVG_PERIOD,"FLL_AVG_PERIOD",0,4,CHIP_UNSIGNED); + + /* FLLFREQWD */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_FLLFREQWD,"FLLFREQWD",0xf314,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x20); + ChipAddField(hChip,RSTB0899_FLLFREQWD,FSTB0899_FLL_FREQ_WD,"FLL_FREQ_WD",0,32,CHIP_UNSIGNED); + + /* ANTIALIASSEL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_ANTIALIASSEL,"ANTIALIASSEL",0xf358,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x20); + ChipAddField(hChip,RSTB0899_ANTIALIASSEL,FSTB0899_ANTI_ALIAS_SEL,"ANTI_ALIAS_SEL",0,2,CHIP_UNSIGNED); + + /* RRCALPHA */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_RRCALPHA,"RRCALPHA",0xf35c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x20); + ChipAddField(hChip,RSTB0899_RRCALPHA,FSTB0899_RRC_ALPHA,"RRC_ALPHA",0,2,CHIP_UNSIGNED); + + /* DCADAPTISHFT */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DCADAPTISHFT,"DCADAPTISHFT",0xf360,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x20); + ChipAddField(hChip,RSTB0899_DCADAPTISHFT,FSTB0899_DC_ADAPT_ISHFT,"DC_ADAPT_ISHFT",0,3,CHIP_UNSIGNED); + + /* IMBOFFSET */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_IMBOFFSET,"IMBOFFSET",0xf364,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x20); + ChipAddField(hChip,RSTB0899_IMBOFFSET,FSTB0899_PHS_IMB_COMP,"PHS_IMB_COMP",8,8,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IMBOFFSET,FSTB0899_AMPL_IMB_COMP,"AMPL_IMB_COMP",0,8,CHIP_UNSIGNED); + + /* IMBESTIMATE */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_IMBESTIMATE,"IMBESTIMATE",0xf368,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x20); + ChipAddField(hChip,RSTB0899_IMBESTIMATE,FSTB0899_PHS_IMB_ESTIMATE,"PHS_IMB_ESTIMATE",8,8,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IMBESTIMATE,FSTB0899_AMPL_IMB_ESTIMATE,"AMPL_IMB_ESTIMATE",0,8,CHIP_UNSIGNED); + + /* IMBCNTRL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_IMBCNTRL,"IMBCNTRL",0xf36c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x20); + ChipAddField(hChip,RSTB0899_IMBCNTRL,FSTB0899_PHS_ADAPT_ISHFT,"PHS_ADAPT_ISHFT",4,3,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IMBCNTRL,FSTB0899_AMPL_ADAPT_ISHFT,"AMPL_ADAPT_ISHFT",1,3,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IMBCNTRL,FSTB0899_IMB_COMP,"IMB_COMP",0,1,CHIP_UNSIGNED); + + /* IFAGCCNTRL2 */ + ChipAddReg(hChip,STCHIP_REG_24,RSTB0899_IFAGCCNTRL2,"IFAGCCNTRL2",0xf374,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x20); + ChipAddField(hChip,RSTB0899_IFAGCCNTRL2,FSTB0899_IF_AGCLOCK_THRESH,"IF_AGCLOCK_THRESH",11,8,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IFAGCCNTRL2,FSTB0899_IF_AGC_SDDIV,"IF_AGC_SDDIV",3,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IFAGCCNTRL2,FSTB0899_IF_AGC_DUMPPER,"IF_AGC_DUMPPER",0,3,CHIP_UNSIGNED); + + /* DMDCNTRL2 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DMDCNTRL2,"DMDCNTRL2",0xf378,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x20); + ChipAddField(hChip,RSTB0899_DMDCNTRL2,FSTB0899_SPECTRUM_INVERT,"SPECTRUM_INVERT",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DMDCNTRL2,FSTB0899_AGC_MODE,"AGC_MODE",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DMDCNTRL2,FSTB0899_CRL_FREQ_ADJ,"CRL_FREQ_ADJ",0,1,CHIP_UNSIGNED); + + /* TPBUFFER */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER,"TPBUFFER",0xf300,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER,FSTB0899_TP_BUFFER_IN,"TP_BUFFER_IN",0,16,CHIP_UNSIGNED); + + /* TPBUFFER1 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER1,"TPBUFFER1",0xf304,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER1,FSTB0899_TP_BUFFER_IN1,"TP_BUFFER_IN1",0,16,CHIP_UNSIGNED); + + /* TPBUFFER2 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER2,"TPBUFFER2",0xf308,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER2,FSTB0899_TP_BUFFER_IN2,"TP_BUFFER_IN2",0,16,CHIP_UNSIGNED); + + /* TPBUFFER3 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER3,"TPBUFFER3",0xf30c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER3,FSTB0899_TP_BUFFER_IN3,"TP_BUFFER_IN3",0,16,CHIP_UNSIGNED); + + /* TPBUFFER4 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER4,"TPBUFFER4",0xf310,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER4,FSTB0899_TP_BUFFER_IN4,"TP_BUFFER_IN4",0,16,CHIP_UNSIGNED); + + /* TPBUFFER5 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER5,"TPBUFFER5",0xf314,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER5,FSTB0899_TP_BUFFER_IN5,"TP_BUFFER_IN5",0,16,CHIP_UNSIGNED); + + /* TPBUFFER6 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER6,"TPBUFFER6",0xf318,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER6,FSTB0899_TP_BUFFER_IN6,"TP_BUFFER_IN6",0,16,CHIP_UNSIGNED); + + /* TPBUFFER7 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER7,"TPBUFFER7",0xf31c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER7,FSTB0899_TP_BUFFER_IN7,"TP_BUFFER_IN7",0,16,CHIP_UNSIGNED); + + /* TPBUFFER8 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER8,"TPBUFFER8",0xf320,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER8,FSTB0899_TP_BUFFER_IN8,"TP_BUFFER_IN8",0,16,CHIP_UNSIGNED); + + /* TPBUFFER9 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER9,"TPBUFFER9",0xf324,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER9,FSTB0899_TP_BUFFER_IN9,"TP_BUFFER_IN9",0,16,CHIP_UNSIGNED); + + /* TPBUFFER10 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER10,"TPBUFFER10",0xf328,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER10,FSTB0899_TP_BUFFER_IN10,"TP_BUFFER_IN10",0,16,CHIP_UNSIGNED); + + /* TPBUFFER11 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER11,"TPBUFFER11",0xf32c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER11,FSTB0899_TP_BUFFER_IN11,"TP_BUFFER_IN11",0,16,CHIP_UNSIGNED); + + /* TPBUFFER12 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER12,"TPBUFFER12",0xf330,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER12,FSTB0899_TP_BUFFER_IN12,"TP_BUFFER_IN12",0,16,CHIP_UNSIGNED); + + /* TPBUFFER13 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER13,"TPBUFFER13",0xf334,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER13,FSTB0899_TP_BUFFER_IN13,"TP_BUFFER_IN13",0,16,CHIP_UNSIGNED); + + /* TPBUFFER14 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER14,"TPBUFFER14",0xf338,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER14,FSTB0899_TP_BUFFER_IN14,"TP_BUFFER_IN14",0,16,CHIP_UNSIGNED); + + /* TPBUFFER15 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER15,"TPBUFFER15",0xf33c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER15,FSTB0899_TP_BUFFER_IN15,"TP_BUFFER_IN15",0,16,CHIP_UNSIGNED); + + /* TPBUFFER16 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER16,"TPBUFFER16",0xf340,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER16,FSTB0899_TP_BUFFER_IN16,"TP_BUFFER_IN16",0,16,CHIP_UNSIGNED); + + /* TPBUFFER17 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER17,"TPBUFFER17",0xf344,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER17,FSTB0899_TP_BUFFER_IN17,"TP_BUFFER_IN17",0,16,CHIP_UNSIGNED); + + /* TPBUFFER18 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER18,"TPBUFFER18",0xf348,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER18,FSTB0899_TP_BUFFER_IN18,"TP_BUFFER_IN18",0,16,CHIP_UNSIGNED); + + /* TPBUFFER19 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER19,"TPBUFFER19",0xf34c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER19,FSTB0899_TP_BUFFER_IN19,"TP_BUFFER_IN19",0,16,CHIP_UNSIGNED); + + /* TPBUFFER20 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER20,"TPBUFFER20",0xf350,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER20,FSTB0899_TP_BUFFER_IN20,"TP_BUFFER_IN20",0,16,CHIP_UNSIGNED); + + /* TPBUFFER21 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER21,"TPBUFFER21",0xf354,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER21,FSTB0899_TP_BUFFER_IN21,"TP_BUFFER_IN21",0,16,CHIP_UNSIGNED); + + /* TPBUFFER22 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER22,"TPBUFFER22",0xf358,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER22,FSTB0899_TP_BUFFER_IN22,"TP_BUFFER_IN22",0,16,CHIP_UNSIGNED); + + /* TPBUFFER23 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER23,"TPBUFFER23",0xf35c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER23,FSTB0899_TP_BUFFER_IN23,"TP_BUFFER_IN23",0,16,CHIP_UNSIGNED); + + /* TPBUFFER24 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER24,"TPBUFFER24",0xf360,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER24,FSTB0899_TP_BUFFER_IN24,"TP_BUFFER_IN24",0,16,CHIP_UNSIGNED); + + /* TPBUFFER25 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER25,"TPBUFFER25",0xf364,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER25,FSTB0899_TP_BUFFER_IN25,"TP_BUFFER_IN25",0,16,CHIP_UNSIGNED); + + /* TPBUFFER26 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER26,"TPBUFFER26",0xf368,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER26,FSTB0899_TP_BUFFER_IN26,"TP_BUFFER_IN26",0,16,CHIP_UNSIGNED); + + /* TPBUFFER27 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER27,"TPBUFFER27",0xf36c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER27,FSTB0899_TP_BUFFER_IN27,"TP_BUFFER_IN27",0,16,CHIP_UNSIGNED); + + /* TPBUFFER28 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER28,"TPBUFFER28",0xf370,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER28,FSTB0899_TP_BUFFER_IN28,"TP_BUFFER_IN28",0,16,CHIP_UNSIGNED); + + /* TPBUFFER29 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER29,"TPBUFFER29",0xf374,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER29,FSTB0899_TP_BUFFER_IN29,"TP_BUFFER_IN29",0,16,CHIP_UNSIGNED); + + /* TPBUFFER30 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER30,"TPBUFFER30",0xf378,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER30,FSTB0899_TP_BUFFER_IN30,"TP_BUFFER_IN30",0,16,CHIP_UNSIGNED); + + /* TPBUFFER31 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER31,"TPBUFFER31",0xf37c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x40); + ChipAddField(hChip,RSTB0899_TPBUFFER31,FSTB0899_TP_BUFFER_IN31,"TP_BUFFER_IN31",0,16,CHIP_UNSIGNED); + + /* TPBUFFER32 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER32,"TPBUFFER32",0xf300,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER32,FSTB0899_TP_BUFFER_IN32,"TP_BUFFER_IN32",0,16,CHIP_UNSIGNED); + + /* TPBUFFER33 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER33,"TPBUFFER33",0xf304,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER33,FSTB0899_TP_BUFFER_IN33,"TP_BUFFER_IN33",0,16,CHIP_UNSIGNED); + + /* TPBUFFER34 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER34,"TPBUFFER34",0xf308,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER34,FSTB0899_TP_BUFFER_IN34,"TP_BUFFER_IN34",0,16,CHIP_UNSIGNED); + + /* TPBUFFER35 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER35,"TPBUFFER35",0xf30c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER35,FSTB0899_TP_BUFFER_IN35,"TP_BUFFER_IN35",0,16,CHIP_UNSIGNED); + + /* TPBUFFER36 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER36,"TPBUFFER36",0xf310,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER36,FSTB0899_TP_BUFFER_IN36,"TP_BUFFER_IN36",0,16,CHIP_UNSIGNED); + + /* TPBUFFER37 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER37,"TPBUFFER37",0xf314,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER37,FSTB0899_TP_BUFFER_IN37,"TP_BUFFER_IN37",0,16,CHIP_UNSIGNED); + + /* TPBUFFER38 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER38,"TPBUFFER38",0xf318,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER38,FSTB0899_TP_BUFFER_IN38,"TP_BUFFER_IN38",0,16,CHIP_UNSIGNED); + + /* TPBUFFER39 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER39,"TPBUFFER39",0xf31c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER39,FSTB0899_TP_BUFFER_IN39,"TP_BUFFER_IN39",0,16,CHIP_UNSIGNED); + + /* TPBUFFER40 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER40,"TPBUFFER40",0xf320,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER40,FSTB0899_TP_BUFFER_IN40,"TP_BUFFER_IN40",0,16,CHIP_UNSIGNED); + + /* TPBUFFER41 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER41,"TPBUFFER41",0xf324,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER41,FSTB0899_TP_BUFFER_IN41,"TP_BUFFER_IN41",0,16,CHIP_UNSIGNED); + + /* TPBUFFER42 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER42,"TPBUFFER42",0xf328,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER42,FSTB0899_TP_BUFFER_IN42,"TP_BUFFER_IN42",0,16,CHIP_UNSIGNED); + + /* TPBUFFER43 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER43,"TPBUFFER43",0xf32c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER43,FSTB0899_TP_BUFFER_IN43,"TP_BUFFER_IN43",0,16,CHIP_UNSIGNED); + + /* TPBUFFER44 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER44,"TPBUFFER44",0xf330,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER44,FSTB0899_TP_BUFFER_IN44,"TP_BUFFER_IN44",0,16,CHIP_UNSIGNED); + + /* TPBUFFER45 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER45,"TPBUFFER45",0xf334,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER45,FSTB0899_TP_BUFFER_IN45,"TP_BUFFER_IN45",0,16,CHIP_UNSIGNED); + + /* TPBUFFER46 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER46,"TPBUFFER46",0xf338,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER46,FSTB0899_TP_BUFFER_IN46,"TP_BUFFER_IN46",0,16,CHIP_UNSIGNED); + + /* TPBUFFER47 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER47,"TPBUFFER47",0xf33c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER47,FSTB0899_TP_BUFFER_IN47,"TP_BUFFER_IN47",0,16,CHIP_UNSIGNED); + + /* TPBUFFER48 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER48,"TPBUFFER48",0xf340,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER48,FSTB0899_TP_BUFFER_IN48,"TP_BUFFER_IN48",0,16,CHIP_UNSIGNED); + + /* TPBUFFER49 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER49,"TPBUFFER49",0xf344,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER49,FSTB0899_TP_BUFFER_IN49,"TP_BUFFER_IN49",0,16,CHIP_UNSIGNED); + + /* TPBUFFER50 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER50,"TPBUFFER50",0xf348,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER50,FSTB0899_TP_BUFFER_IN50,"TP_BUFFER_IN50",0,16,CHIP_UNSIGNED); + + /* TPBUFFER51 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER51,"TPBUFFER51",0xf34c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER51,FSTB0899_TP_BUFFER_IN51,"TP_BUFFER_IN51",0,16,CHIP_UNSIGNED); + + /* TPBUFFER52 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER52,"TPBUFFER52",0xf350,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER52,FSTB0899_TP_BUFFER_IN52,"TP_BUFFER_IN52",0,16,CHIP_UNSIGNED); + + /* TPBUFFER53 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER53,"TPBUFFER53",0xf354,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER53,FSTB0899_TP_BUFFER_IN53,"TP_BUFFER_IN53",0,16,CHIP_UNSIGNED); + + /* TPBUFFER54 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER54,"TPBUFFER54",0xf358,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER54,FSTB0899_TP_BUFFER_IN54,"TP_BUFFER_IN54",0,16,CHIP_UNSIGNED); + + /* TPBUFFER55 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER55,"TPBUFFER55",0xf35c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER55,FSTB0899_TP_BUFFER_IN55,"TP_BUFFER_IN55",0,16,CHIP_UNSIGNED); + + /* TPBUFFER56 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER56,"TPBUFFER56",0xf360,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER56,FSTB0899_TP_BUFFER_IN56,"TP_BUFFER_IN56",0,16,CHIP_UNSIGNED); + + /* TPBUFFER57 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER57,"TPBUFFER57",0xf364,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER57,FSTB0899_TP_BUFFER_IN57,"TP_BUFFER_IN57",0,16,CHIP_UNSIGNED); + + /* TPBUFFER58 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER58,"TPBUFFER58",0xf368,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER58,FSTB0899_TP_BUFFER_IN58,"TP_BUFFER_IN58",0,16,CHIP_UNSIGNED); + + /* TPBUFFER59 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER59,"TPBUFFER59",0xf36c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER59,FSTB0899_TP_BUFFER_IN59,"TP_BUFFER_IN59",0,16,CHIP_UNSIGNED); + + /* TPBUFFER60 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER60,"TPBUFFER60",0xf370,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER60,FSTB0899_TP_BUFFER_IN60,"TP_BUFFER_IN60",0,16,CHIP_UNSIGNED); + + /* TPBUFFER61 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER61,"TPBUFFER61",0xf374,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER61,FSTB0899_TP_BUFFER_IN61,"TP_BUFFER_IN61",0,16,CHIP_UNSIGNED); + + /* TPBUFFER62 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER62,"TPBUFFER62",0xf378,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER62,FSTB0899_TP_BUFFER_IN62,"TP_BUFFER_IN62",0,16,CHIP_UNSIGNED); + + /* TPBUFFER63 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_TPBUFFER63,"TPBUFFER63",0xf37c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x60); + ChipAddField(hChip,RSTB0899_TPBUFFER63,FSTB0899_TP_BUFFER_IN63,"TP_BUFFER_IN63",0,16,CHIP_UNSIGNED); + + /* RESETCNTRL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_RESETCNTRL,"RESETCNTRL",0xf300,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_RESETCNTRL,FSTB0899_DVBS2_SRST,"DVBS2_SRST",0,1,CHIP_UNSIGNED); + + /* ACMENABLE */ + ChipAddReg(hChip,STCHIP_REG_24,RSTB0899_ACMENABLE,"ACMENABLE",0xf304,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_ACMENABLE,FSTB0899_ACM_ENABLE,"ACM_ENABLE",0,1,CHIP_UNSIGNED); + + /* DESCRCNTRL */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_DESCRCNTRL,"DESCRCNTRL",0xf30c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_DESCRCNTRL,FSTB0899_DESCR_CNTRL,"DESCR_CNTRL",0,16,CHIP_UNSIGNED); + + /* CSMCNTRL1 */ + ChipAddReg(hChip,STCHIP_REG_24,RSTB0899_CSMCNTRL1,"CSMCNTRL1",0xf310,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_CSMCNTRL1,FSTB0899_FORCE_FREQLOCK_STATE,"FORCE_FREQLOCK_STATE",19,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CSMCNTRL1,FSTB0899_FREQLOCK_STATE,"FREQLOCK_STATE",18,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CSMCNTRL1,FSTB0899_AUTO_PARAM,"AUTO_PARAM",17,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CSMCNTRL1,FSTB0899_FE_LOOP_SHIFT,"FE_LOOP_SHIFT",14,3,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CSMCNTRL1,FSTB0899_CSM_AGC_SHIFT,"CSM_AGC_SHIFT",11,3,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CSMCNTRL1,FSTB0899_CSM_AGC_GAIN,"CSM_AGC_GAIN",2,9,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CSMCNTRL1,FSTB0899_CSM_TOW_PASS,"CSM_TOW_PASS",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CSMCNTRL1,FSTB0899_CSM_DVT_TABLE,"CSM_DVT_TABLE",0,1,CHIP_UNSIGNED); + + /* CSMCNTRL2 */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_CSMCNTRL2,"CSMCNTRL2",0xf314,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_CSMCNTRL2,FSTB0899_CSM_GAMMA_RHOACQ,"CSM_GAMMA_RHOACQ",8,17,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CSMCNTRL2,FSTB0899_CSM_GAMMA_ACQ,"CSM_GAMMA_ACQ",0,8,CHIP_UNSIGNED); + + /* CSMCNTRL3 */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_CSMCNTRL3,"CSMCNTRL3",0xf318,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_CSMCNTRL3,FSTB0899_CSM_GAMMA_RHOTRACK,"CSM_GAMMA_RHOTRACK",8,17,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CSMCNTRL3,FSTB0899_CSM_GAMMA_TRACK,"CSM_GAMMA_TRACK",0,8,CHIP_UNSIGNED); + + /* CSMCNTRL4 */ + ChipAddReg(hChip,STCHIP_REG_24,RSTB0899_CSMCNTRL4,"CSMCNTRL4",0xf31c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_CSMCNTRL4,FSTB0899_PHASE_DIFF_THRESHOLD,"PHASE_DIFF_THRESHOLD",8,11,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CSMCNTRL4,FSTB0899_LOCK_COUNT_THRESHOLD,"LOCK_COUNT_THRESHOLD",0,8,CHIP_UNSIGNED); + + /* UWPCNTRL1 */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_UWPCNTRL1,"UWPCNTRL1",0xf320,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_UWPCNTRL1,FSTB0899_UWP_THRESHOLD_SOF,"UWP_THRESHOLD_SOF",11,15,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_UWPCNTRL1,FSTB0899_UWP_ESN0_QUANT,"UWP_ESN0_QUANT",3,8,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_UWPCNTRL1,FSTB0899_UWP_ESN0_AVE,"UWP_ESN0_AVE",1,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_UWPCNTRL1,FSTB0899_UWP_START,"UWP_START",0,1,CHIP_UNSIGNED); + + /* UWPCNTRL2 */ + ChipAddReg(hChip,STCHIP_REG_24,RSTB0899_UWPCNTRL2,"UWPCNTRL2",0xf324,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_UWPCNTRL2,FSTB0899_UWP_MISS_THRESHOLD,"UWP_MISS_THRESHOLD",16,8,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_UWPCNTRL2,FSTB0899_FE_FINE_TRK,"FE_FINE_TRK",8,8,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_UWPCNTRL2,FSTB0899_FE_COARSE_TRK,"FE_COARSE_TRK",0,8,CHIP_UNSIGNED); + + /* UWPSTAT1 */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_UWPSTAT1,"UWPSTAT1",0xf328,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_UWPSTAT1,FSTB0899_UWP_STATE,"UWP_STATE",15,10,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_UWPSTAT1,FSTB0899_UW_MAX_PEAK,"UW_MAX_PEAK",0,15,CHIP_UNSIGNED); + + /* UWPSTAT2 */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_UWPSTAT2,"UWPSTAT2",0xf32c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_UWPSTAT2,FSTB0899_ESN0_ESR,"ESN0_ESR",7,19,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_UWPSTAT2,FSTB0899_UWP_DECODED_MODCODE,"UWP_DECODED_MODCODE",0,7,CHIP_UNSIGNED); + + /* DMDSTAT2 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DMDSTAT2,"DMDSTAT2",0xf340,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_DMDSTAT2,FSTB0899_CSM_LOCK,"CSM_LOCK",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DMDSTAT2,FSTB0899_UWP_LOCK,"UWP_LOCK",0,1,CHIP_UNSIGNED); + + /* FREQADJSCALE */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_FREQADJSCALE,"FREQADJSCALE",0xf344,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_FREQADJSCALE,FSTB0899_FREQ_ADJ_SCALE,"FREQ_ADJ_SCALE",0,12,CHIP_UNSIGNED); + + /* UWPCNTRL3 */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_UWPCNTRL3,"UWPCNTRL3",0xf34c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_UWPCNTRL3,FSTB0899_UWP_THRESHOLD_TRACK,"UWP_THRESHOLD_TRACK",15,15,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_UWPCNTRL3,FSTB0899_UWP_THRESHOLD_ACQ,"UWP_THRESHOLD_ACQ",0,15,CHIP_UNSIGNED); + + /* SYMCLKSEL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_SYMCLKSEL,"SYMCLKSEL",0xf350,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_SYMCLKSEL,FSTB0899_SYM_CLK_SEL,"SYM_CLK_SEL",0,2,CHIP_UNSIGNED); + + /* SOFSRCHTO */ + ChipAddReg(hChip,STCHIP_REG_24,RSTB0899_SOFSRCHTO,"SOFSRCHTO",0xf354,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_SOFSRCHTO,FSTB0899_SOF_SEARCH_TIMEOUT,"SOF_SEARCH_TIMEOUT",0,22,CHIP_SIGNED); + + /* ACQCNTRL1 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_ACQCNTRL1,"ACQCNTRL1",0xf358,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_ACQCNTRL1,FSTB0899_FE_FINE_ACQ,"FE_FINE_ACQ",8,8,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_ACQCNTRL1,FSTB0899_FE_CORASE_ACQ,"FE_CORASE_ACQ",0,8,CHIP_UNSIGNED); + + /* ACQCNTRL2 */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_ACQCNTRL2,"ACQCNTRL2",0xf35c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_ACQCNTRL2,FSTB0899_ZIGZAG,"ZIGZAG",25,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_ACQCNTRL2,FSTB0899_NUM_STEPS,"NUM_STEPS",17,8,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_ACQCNTRL2,FSTB0899_FREQ_STEP_SIZE,"FREQ_STEP_SIZE",0,17,CHIP_UNSIGNED); + + /* ACQCNTRL3 */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_ACQCNTRL3,"ACQCNTRL3",0xf360,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_ACQCNTRL3,FSTB0899_THRESHOLD_SCL,"THRESHOLD_SCL",23,6,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_ACQCNTRL3,FSTB0899_UWP_THRESHOLD_SRCH,"UWP_THRESHOLD_SRCH",8,15,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_ACQCNTRL3,FSTB0899_AUTO_REACQUIRE,"AUTO_REACQUIRE",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_ACQCNTRL3,FSTB0899_TRACK_LOCK_SEL,"TRACK_LOCK_SEL",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_ACQCNTRL3,FSTB0899_ACQ_SEARCH_MODE,"ACQ_SEARCH_MODE",4,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_ACQCNTRL3,FSTB0899_CONFIRM_FRAMES,"CONFIRM_FRAMES",0,4,CHIP_UNSIGNED); + + /* FESETTLE */ + ChipAddReg(hChip,STCHIP_REG_24,RSTB0899_FESETTLE,"FESETTLE",0xf364,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_FESETTLE,FSTB0899_SETTING_TIME,"SETTING_TIME",0,22,CHIP_UNSIGNED); + + /* ACDWELL */ + ChipAddReg(hChip,STCHIP_REG_24,RSTB0899_ACDWELL,"ACDWELL",0xf368,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_ACDWELL,FSTB0899_DWELL_TIME,"DWELL_TIME",0,22,CHIP_UNSIGNED); + + /* ACQUIRETRIG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_ACQUIRETRIG,"ACQUIRETRIG",0xf36c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_ACQUIRETRIG,FSTB0899_ACQUIRE,"ACQUIRE",0,1,CHIP_UNSIGNED); + + /* LOCKLOST */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_LOCKLOST,"LOCKLOST",0xf370,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_LOCKLOST,FSTB0899_LOCK_LOST,"LOCK_LOST",0,1,CHIP_UNSIGNED); + + /* ACQSTAT1 */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_ACQSTAT1,"ACQSTAT1",0xf374,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_ACQSTAT1,FSTB0899_STEP_FREQ,"STEP_FREQ",11,21,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_ACQSTAT1,FSTB0899_ACQ_STATE,"ACQ_STATE",8,3,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_ACQSTAT1,FSTB0899_UW_DETECT_COUNT,"UW_DETECT_COUNT",0,8,CHIP_UNSIGNED); + + /* ACQTIMEOUT */ + ChipAddReg(hChip,STCHIP_REG_24,RSTB0899_ACQTIMEOUT,"ACQTIMEOUT",0xf378,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_ACQTIMEOUT,FSTB0899_ACQ_TIMEOUT,"ACQ_TIMEOUT",0,22,CHIP_UNSIGNED); + + /* ACQTIME */ + ChipAddReg(hChip,STCHIP_REG_24,RSTB0899_ACQTIME,"ACQTIME",0xf37c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x400); + ChipAddField(hChip,RSTB0899_ACQTIME,FSTB0899_ACQ_TIME_SYM,"ACQ_TIME_SYM",0,24,CHIP_UNSIGNED); + + /* FINALAGCCNTRL */ + ChipAddReg(hChip,STCHIP_REG_32,RSTB0899_FINALAGCCNTRL,"FINALAGCCNTRL",0xf308,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_FINALAGCCNTRL,FSTB0899_FINAL_GAIN_INIT,"FINAL_GAIN_INIT",12,14,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_FINALAGCCNTRL,FSTB0899_FINAL_LOOP_GAIN,"FINAL_LOOP_GAIN",8,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_FINALAGCCNTRL,FSTB0899_FINAL_LDGAIN_INIT,"FINAL_LDGAIN_INIT",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_FINALAGCCNTRL,FSTB0899_FINAL_AGC_REF,"FINAL_AGC_REF",0,7,CHIP_UNSIGNED); + + /* FINALAGCCGAIN */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_FINALAGCCGAIN,"FINALAGCCGAIN",0xf30c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_FINALAGCCGAIN,FSTB0899_FINAL_AGC_GAIN,"FINAL_AGC_GAIN",0,14,CHIP_UNSIGNED); + + /* EQUILIZERINIT */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_EQUILIZERINIT,"EQUILIZERINIT",0xf310,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQUILIZERINIT,FSTB0899_EQ_SRST,"EQ_SRST",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_EQUILIZERINIT,FSTB0899_EQ_INIT,"EQ_INIT",0,1,CHIP_UNSIGNED); + + /* EQCNTL */ + ChipAddReg(hChip,STCHIP_REG_24,RSTB0899_EQCNTL,"EQCNTL",0xf314,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQCNTL,FSTB0899_EQ_ADAPT_MODE,"EQ_ADAPT_MODE",18,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_EQCNTL,FSTB0899_EQ_DELAY,"EQ_DELAY",14,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_EQCNTL,FSTB0899_EQ_QUANT_LEVEL,"EQ_QUANT_LEVEL",6,8,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_EQCNTL,FSTB0899_EQ_DISABLE_UPDATE,"EQ_DISABLE_UPDATE",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_EQCNTL,FSTB0899_EQ_BYPASS,"EQ_BYPASS",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_EQCNTL,FSTB0899_EQ_SHIFT,"EQ_SHIFT",0,4,CHIP_UNSIGNED); + + /* EQIINITCOEFF0 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQIINITCOEFF0,"EQIINITCOEFF0",0xf320,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQIINITCOEFF0,FSTB0899_EQ_I_INITCOEFF0,"EQ_I_INITCOEFF0",0,12,CHIP_UNSIGNED); + + /* EQIINITCOEFF1 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQIINITCOEFF1,"EQIINITCOEFF1",0xf324,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQIINITCOEFF1,FSTB0899_EQ_I_INITCOEFF1,"EQ_I_INITCOEFF1",0,12,CHIP_SIGNED); + + /* EQIINITCOEFF2 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQIINITCOEFF2,"EQIINITCOEFF2",0xf328,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQIINITCOEFF2,FSTB0899_EQ_I_INITCOEFF2,"EQ_I_INITCOEFF2",0,12,CHIP_SIGNED); + + /* EQIINITCOEFF3 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQIINITCOEFF3,"EQIINITCOEFF3",0xf32c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQIINITCOEFF3,FSTB0899_EQ_I_INITCOEFF3,"EQ_I_INITCOEFF3",0,12,CHIP_SIGNED); + + /* EQIINITCOEFF4 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQIINITCOEFF4,"EQIINITCOEFF4",0xf330,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQIINITCOEFF4,FSTB0899_EQ_I_INITCOEFF4,"EQ_I_INITCOEFF4",0,12,CHIP_SIGNED); + + /* EQIINITCOEFF5 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQIINITCOEFF5,"EQIINITCOEFF5",0xf334,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQIINITCOEFF5,FSTB0899_EQ_I_INITCOEFF5,"EQ_I_INITCOEFF5",0,12,CHIP_SIGNED); + + /* EQIINITCOEFF6 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQIINITCOEFF6,"EQIINITCOEFF6",0xf338,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQIINITCOEFF6,FSTB0899_EQ_I_INITCOEFF6,"EQ_I_INITCOEFF6",0,12,CHIP_SIGNED); + + /* EQIINITCOEFF7 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQIINITCOEFF7,"EQIINITCOEFF7",0xf33c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQIINITCOEFF7,FSTB0899_EQ_I_INITCOEFF7,"EQ_I_INITCOEFF7",0,12,CHIP_SIGNED); + + /* EQIINITCOEFF8 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQIINITCOEFF8,"EQIINITCOEFF8",0xf340,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQIINITCOEFF8,FSTB0899_EQ_I_INITCOEFF8,"EQ_I_INITCOEFF8",0,12,CHIP_SIGNED); + + /* EQIINITCOEFF9 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQIINITCOEFF9,"EQIINITCOEFF9",0xf344,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQIINITCOEFF9,FSTB0899_EQ_I_INITCOEFF9,"EQ_I_INITCOEFF9",0,12,CHIP_SIGNED); + + /* EQIINITCOEFF10 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQIINITCOEFF10,"EQIINITCOEFF10",0xf348,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQIINITCOEFF10,FSTB0899_EQ_I_INITCOEFF10,"EQ_I_INITCOEFF10",0,12,CHIP_SIGNED); + + /* EQQINITCOEFF0 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQQINITCOEFF0,"EQQINITCOEFF0",0xf350,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQQINITCOEFF0,FSTB0899_EQ_Q_INITCOEFF0,"EQ_Q_INITCOEFF0",0,12,CHIP_SIGNED); + + /* EQQINITCOEFF1 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQQINITCOEFF1,"EQQINITCOEFF1",0xf354,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQQINITCOEFF1,FSTB0899_EQ_Q_INITCOEFF1,"EQ_Q_INITCOEFF1",0,12,CHIP_SIGNED); + + /* EQQINITCOEFF2 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQQINITCOEFF2,"EQQINITCOEFF2",0xf358,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQQINITCOEFF2,FSTB0899_EQ_Q_INITCOEFF2,"EQ_Q_INITCOEFF2",0,12,CHIP_SIGNED); + + /* EQQINITCOEFF3 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQQINITCOEFF3,"EQQINITCOEFF3",0xf35c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQQINITCOEFF3,FSTB0899_EQ_Q_INITCOEFF3,"EQ_Q_INITCOEFF3",0,12,CHIP_SIGNED); + + /* EQQINITCOEFF4 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQQINITCOEFF4,"EQQINITCOEFF4",0xf360,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQQINITCOEFF4,FSTB0899_EQ_Q_INITCOEFF4,"EQ_Q_INITCOEFF4",0,12,CHIP_SIGNED); + + /* EQQINITCOEFF5 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQQINITCOEFF5,"EQQINITCOEFF5",0xf364,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQQINITCOEFF5,FSTB0899_EQ_Q_INITCOEFF5,"EQ_Q_INITCOEFF5",0,12,CHIP_SIGNED); + + /* EQQINITCOEFF6 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQQINITCOEFF6,"EQQINITCOEFF6",0xf368,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQQINITCOEFF6,FSTB0899_EQ_Q_INITCOEFF6,"EQ_Q_INITCOEFF6",0,12,CHIP_SIGNED); + + /* EQQINITCOEFF7 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQQINITCOEFF7,"EQQINITCOEFF7",0xf36c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQQINITCOEFF7,FSTB0899_EQ_Q_INITCOEFF7,"EQ_Q_INITCOEFF7",0,12,CHIP_SIGNED); + + /* EQQINITCOEFF8 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQQINITCOEFF8,"EQQINITCOEFF8",0xf370,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQQINITCOEFF8,FSTB0899_EQ_Q_INITCOEFF8,"EQ_Q_INITCOEFF8",0,12,CHIP_SIGNED); + + /* EQQINITCOEFF9 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQQINITCOEFF9,"EQQINITCOEFF9",0xf374,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQQINITCOEFF9,FSTB0899_EQ_Q_INITCOEFF9,"EQ_Q_INITCOEFF9",0,12,CHIP_SIGNED); + + /* EQQINITCOEFF10 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQQINITCOEFF10,"EQQINITCOEFF10",0xf378,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x440); + ChipAddField(hChip,RSTB0899_EQQINITCOEFF10,FSTB0899_EQ_Q_INITCOEFF10,"EQ_Q_INITCOEFF10",0,12,CHIP_SIGNED); + + /* EQICOEFFSOUT0 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQICOEFFSOUT0,"EQICOEFFSOUT0",0xf300,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x460); + ChipAddField(hChip,RSTB0899_EQICOEFFSOUT0,FSTB0899_EQ_I_COEFFOUT0,"EQ_I_COEFFOUT0",0,12,CHIP_SIGNED); + + /* EQICOEFFSOUT1 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQICOEFFSOUT1,"EQICOEFFSOUT1",0xf304,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x460); + ChipAddField(hChip,RSTB0899_EQICOEFFSOUT1,FSTB0899_EQ_I_COEFFOUT1,"EQ_I_COEFFOUT1",0,12,CHIP_SIGNED); + + /* EQICOEFFSOUT2 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQICOEFFSOUT2,"EQICOEFFSOUT2",0xf308,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x460); + ChipAddField(hChip,RSTB0899_EQICOEFFSOUT2,FSTB0899_EQ_I_COEFFOUT2,"EQ_I_COEFFOUT2",0,12,CHIP_SIGNED); + + /* EQICOEFFSOUT3 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQICOEFFSOUT3,"EQICOEFFSOUT3",0xf30c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x460); + ChipAddField(hChip,RSTB0899_EQICOEFFSOUT3,FSTB0899_EQ_I_COEFFOUT3,"EQ_I_COEFFOUT3",0,12,CHIP_SIGNED); + + /* EQICOEFFSOUT4 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQICOEFFSOUT4,"EQICOEFFSOUT4",0xf310,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x460); + ChipAddField(hChip,RSTB0899_EQICOEFFSOUT4,FSTB0899_EQ_I_COEFFOUT4,"EQ_I_COEFFOUT4",0,12,CHIP_SIGNED); + + /* EQICOEFFSOUT5 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQICOEFFSOUT5,"EQICOEFFSOUT5",0xf314,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x460); + ChipAddField(hChip,RSTB0899_EQICOEFFSOUT5,FSTB0899_EQ_I_COEFFOUT5,"EQ_I_COEFFOUT5",0,12,CHIP_SIGNED); + + /* EQICOEFFSOUT6 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQICOEFFSOUT6,"EQICOEFFSOUT6",0xf318,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x460); + ChipAddField(hChip,RSTB0899_EQICOEFFSOUT6,FSTB0899_EQ_I_COEFFOUT6,"EQ_I_COEFFOUT6",0,12,CHIP_SIGNED); + + /* EQICOEFFSOUT7 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQICOEFFSOUT7,"EQICOEFFSOUT7",0xf31c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x460); + ChipAddField(hChip,RSTB0899_EQICOEFFSOUT7,FSTB0899_EQ_I_COEFFOUT7,"EQ_I_COEFFOUT7",0,12,CHIP_SIGNED); + + /* EQICOEFFSOUT8 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQICOEFFSOUT8,"EQICOEFFSOUT8",0xf320,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x460); + ChipAddField(hChip,RSTB0899_EQICOEFFSOUT8,FSTB0899_EQ_I_COEFFOUT8,"EQ_I_COEFFOUT8",0,12,CHIP_SIGNED); + + /* EQICOEFFSOUT9 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQICOEFFSOUT9,"EQICOEFFSOUT9",0xf324,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x460); + ChipAddField(hChip,RSTB0899_EQICOEFFSOUT9,FSTB0899_EQ_I_COEFFOUT9,"EQ_I_COEFFOUT9",0,12,CHIP_SIGNED); + + /* EQICOEFFSOUT10 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQICOEFFSOUT10,"EQICOEFFSOUT10",0xf328,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x460); + ChipAddField(hChip,RSTB0899_EQICOEFFSOUT10,FSTB0899_EQ_I_COEFFOUT10,"EQ_I_COEFFOUT10",0,12,CHIP_SIGNED); + + /* EQQCOEFFSOUT0 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQQCOEFFSOUT0,"EQQCOEFFSOUT0",0xf330,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x460); + ChipAddField(hChip,RSTB0899_EQQCOEFFSOUT0,FSTB0899_EQ_Q_COEFFOUT0,"EQ_Q_COEFFOUT0",0,12,CHIP_SIGNED); + + /* EQQCOEFFSOUT1 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQQCOEFFSOUT1,"EQQCOEFFSOUT1",0xf334,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x460); + ChipAddField(hChip,RSTB0899_EQQCOEFFSOUT1,FSTB0899_EQ_Q_COEFFOUT1,"EQ_Q_COEFFOUT1",0,12,CHIP_SIGNED); + + /* EQQCOEFFSOUT2 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQQCOEFFSOUT2,"EQQCOEFFSOUT2",0xf338,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x460); + ChipAddField(hChip,RSTB0899_EQQCOEFFSOUT2,FSTB0899_EQ_Q_COEFFOUT2,"EQ_Q_COEFFOUT2",0,12,CHIP_SIGNED); + + /* EQQCOEFFSOUT3 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQQCOEFFSOUT3,"EQQCOEFFSOUT3",0xf33c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x460); + ChipAddField(hChip,RSTB0899_EQQCOEFFSOUT3,FSTB0899_EQ_Q_COEFFOUT3,"EQ_Q_COEFFOUT3",0,12,CHIP_SIGNED); + + /* EQQCOEFFSOUT4 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQQCOEFFSOUT4,"EQQCOEFFSOUT4",0xf340,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x460); + ChipAddField(hChip,RSTB0899_EQQCOEFFSOUT4,FSTB0899_EQ_Q_COEFFOUT4,"EQ_Q_COEFFOUT4",0,12,CHIP_SIGNED); + + /* EQQCOEFFSOUT5 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQQCOEFFSOUT5,"EQQCOEFFSOUT5",0xf344,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x460); + ChipAddField(hChip,RSTB0899_EQQCOEFFSOUT5,FSTB0899_EQ_Q_COEFFOUT5,"EQ_Q_COEFFOUT5",0,12,CHIP_SIGNED); + + /* EQQCOEFFSOUT6 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQQCOEFFSOUT6,"EQQCOEFFSOUT6",0xf348,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x460); + ChipAddField(hChip,RSTB0899_EQQCOEFFSOUT6,FSTB0899_EQ_Q_COEFFOUT6,"EQ_Q_COEFFOUT6",0,12,CHIP_SIGNED); + + /* EQQCOEFFSOUT7 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQQCOEFFSOUT7,"EQQCOEFFSOUT7",0xf34c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x460); + ChipAddField(hChip,RSTB0899_EQQCOEFFSOUT7,FSTB0899_EQ_Q_COEFFOUT7,"EQ_Q_COEFFOUT7",0,12,CHIP_SIGNED); + + /* EQQCOEFFSOUT8 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQQCOEFFSOUT8,"EQQCOEFFSOUT8",0xf350,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x460); + ChipAddField(hChip,RSTB0899_EQQCOEFFSOUT8,FSTB0899_EQ_Q_COEFFOUT8,"EQ_Q_COEFFOUT8",0,12,CHIP_SIGNED); + + /* EQQCOEFFSOUT9 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQQCOEFFSOUT9,"EQQCOEFFSOUT9",0xf354,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x460); + ChipAddField(hChip,RSTB0899_EQQCOEFFSOUT9,FSTB0899_EQ_Q_COEFFOUT9,"EQ_Q_COEFFOUT9",0,12,CHIP_SIGNED); + + /* EQQCOEFFSOUT10 */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_EQQCOEFFSOUT10,"EQQCOEFFSOUT10",0xf358,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xf3fc,0x460); + ChipAddField(hChip,RSTB0899_EQQCOEFFSOUT10,FSTB0899_EQ_Q_COEFFOUT10,"EQ_Q_COEFFOUT10",0,12,CHIP_SIGNED); + + /* DEMOD */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DEMOD,"DEMOD",0xf40e,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_DEMOD,FSTB0899_DEMOD_RESERVED,"DEMOD_RESERVED",6,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DEMOD,FSTB0899_IQSYMB_SEL,"IQSYMB_SEL",4,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DEMOD,FSTB0899_DEMOD_RESERVED2,"DEMOD_RESERVED2",2,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DEMOD,FSTB0899_DEMOD_RESERVED3,"DEMOD_RESERVED3",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DEMOD,FSTB0899_MODE_COEF,"MODE_COEF",0,1,CHIP_UNSIGNED); + + /* RCOMPC */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_RCOMPC,"RCOMPC",0xf410,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_RCOMPC,FSTB0899_IMBCOMP_ON,"IMBCOMP_ON",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_RCOMPC,FSTB0899_DCADJ_FORCE,"DCADJ_FORCE",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_RCOMPC,FSTB0899_DCCOMP_BETA,"DCCOMP_BETA",3,3,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_RCOMPC,FSTB0899_IMBCOMP_BETA,"IMBCOMP_BETA",0,3,CHIP_UNSIGNED); + + /* AGC1CN */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_AGC1CN,"AGC1CN",0xf412,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_AGC1CN,FSTB0899_AGC1CN_RESERVED,"AGC1CN_RESERVED",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_AGC1CN,FSTB0899_AGCOUT_FAST,"AGCOUT_FAST",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_AGC1CN,FSTB0899_AGC1CN_RESERVED2,"AGC1CN_RESERVED2",3,3,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_AGC1CN,FSTB0899_AGCIQ_BETA1,"AGCIQ_BETA1",0,3,CHIP_UNSIGNED); + + /* AGC1REF */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_AGC1REF,"AGC1REF",0xf413,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_AGC1REF,FSTB0899_AGC1REF_RESERVED,"AGC1REF_RESERVED",6,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_AGC1REF,FSTB0899_AGCIQ_REF,"AGCIQ_REF",0,6,CHIP_UNSIGNED); + + /* RTC */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_RTC,"RTC",0xf417,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_RTC,FSTB0899_ALPHA_TMG,"ALPHA_TMG",4,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_RTC,FSTB0899_BETA_TMG,"BETA_TMG",0,4,CHIP_UNSIGNED); + + /* TMGCFG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TMGCFG,"TMGCFG",0xf418,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TMGCFG,FSTB0899_MODE_150PPM,"MODE_150PPM",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TMGCFG,FSTB0899_FENASAMP,"FENASAMP",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TMGCFG,FSTB0899_TMG_AUTOSRCH,"TMG_AUTOSRCH",4,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TMGCFG,FSTB0899_TMG_RAMPM,"TMG_RAMPM",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TMGCFG,FSTB0899_TMG_SEARCHRANGE,"TMG_SEARCHRANGE",0,3,CHIP_UNSIGNED); + + /* AGC2REF */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_AGC2REF,"AGC2REF",0xf419,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_AGC2REF,FSTB0899_AGC2_COEFF,"AGC2_COEFF",5,3,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_AGC2REF,FSTB0899_AGC2_REF,"AGC2_REF",0,5,CHIP_UNSIGNED); + + /* TLSR */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TLSR,"TLSR",0xf41a,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TLSR,FSTB0899_STEP_MINUS,"STEP_MINUS",4,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TLSR,FSTB0899_STEP_PLUS,"STEP_PLUS",0,4,CHIP_UNSIGNED); + + /* CFD */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_CFD,"CFD",0xf41b,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_CFD,FSTB0899_CFD_ON,"CFD_ON",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CFD,FSTB0899_BETA_FC,"BETA_FC",4,3,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CFD,FSTB0899_FDCT,"FDCT",2,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CFD,FSTB0899_LDL,"LDL",0,2,CHIP_UNSIGNED); + + /* ACLC */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_ACLC,"ACLC",0xf41c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_ACLC,FSTB0899_DEROT_ON_OFF,"DEROT_ON_OFF",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_ACLC,FSTB0899_ACLC,"ACLC",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_ACLC,FSTB0899_NOISE,"NOISE",4,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_ACLC,FSTB0899_ALPHA,"ALPHA",0,4,CHIP_UNSIGNED); + + /* BCLC */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_BCLC,"BCLC",0xf41d,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_BCLC,FSTB0899_ALGO,"ALGO",6,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BCLC,FSTB0899_BETA,"BETA",0,6,CHIP_UNSIGNED); + + /* EQON */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_EQON,"EQON",0xf41e,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_EQON,FSTB0899_EQON_RESERVED,"EQON_RESERVED",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_EQON,FSTB0899_EGAL_ON,"EGAL_ON",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_EQON,FSTB0899_EQON_RESERVED2,"EQON_RESERVED2",0,6,CHIP_UNSIGNED); + + /* LDT */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_LDT,"LDT",0xf41f,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_LDT,FSTB0899_LOCK_THRESHOLD,"LOCK_THRESHOLD",0,8,CHIP_SIGNED); + + /* LDT2 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_LDT2,"LDT2",0xf420,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_LDT2,FSTB0899_LOCK_THRESHOLD2,"LOCK_THRESHOLD2",0,8,CHIP_SIGNED); + + /* EQUALREF */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_EQUALREF,"EQUALREF",0xf425,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_EQUALREF,FSTB0899_RSTEQBEFTOUT,"RSTEQBEFTOUT",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_EQUALREF,FSTB0899_FRSTPLF_PSKCHG,"FRSTPLF_PSKCHG",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_EQUALREF,FSTB0899_RSTEQ_PSKCHG,"RSTEQ_PSKCHG",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_EQUALREF,FSTB0899_EQUALREF_RESERVED,"EQUALREF_RESERVED",0,5,CHIP_UNSIGNED); + + /* TMGRAMP */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TMGRAMP,"TMGRAMP",0xf426,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TMGRAMP,FSTB0899_TMGLOCK_RAMP,"TMGLOCK_RAMP",0,8,CHIP_UNSIGNED); + + /* TMGTHD */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TMGTHD,"TMGTHD",0xf427,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TMGTHD,FSTB0899_TMGLOCK_THR,"TMGLOCK_THR",0,8,CHIP_UNSIGNED); + + /* IDCCOMP */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_IDCCOMP,"IDCCOMP",0xf428,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_IDCCOMP,FSTB0899_IAVERAGE_ADJ,"IAVERAGE_ADJ",1,7,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IDCCOMP,FSTB0899_IDCADJ_FORCE,"IDCADJ_FORCE",0,1,CHIP_UNSIGNED); + + /* QDCCOMP */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_QDCCOMP,"QDCCOMP",0xf429,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_QDCCOMP,FSTB0899_QAVERAGE_ADJ,"QAVERAGE_ADJ",1,7,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_QDCCOMP,FSTB0899_QDCADJ_FORCE,"QDCADJ_FORCE",0,1,CHIP_UNSIGNED); + + /* POWERI */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_POWERI,"POWERI",0xf42a,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_POWERI,FSTB0899_POWER_I,"POWER_I",0,8,CHIP_UNSIGNED); + + /* POWERQ */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_POWERQ,"POWERQ",0xf42b,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_POWERQ,FSTB0899_POWER_Q,"POWER_Q",0,8,CHIP_UNSIGNED); + + /* RCOMP */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_RCOMP,"RCOMP",0xf42c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_RCOMP,FSTB0899_RCOMP_VALUE,"RCOMP_VALUE",0,8,CHIP_UNSIGNED); + + /* AGCIQIN */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_AGCIQIN,"AGCIQIN",0xf42e,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_AGCIQIN,FSTB0899_AGCIQ_VALUE,"AGCIQ_VALUE",0,8,CHIP_SIGNED); + + /* AGC2I1 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_AGC2I1,"AGC2I1",0xf436,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_AGC2I1,FSTB0899_AGC2I_MSB,"AGC2I_MSB",0,8,CHIP_UNSIGNED); + + /* AGC2I2 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_AGC2I2,"AGC2I2",0xf437,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_AGC2I2,FSTB0899_AGC2I_LSB,"AGC2I_LSB",0,8,CHIP_UNSIGNED); + + /* TLIR */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TLIR,"TLIR",0xf438,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TLIR,FSTB0899_TMG_LOCK_IND,"TMG_LOCK_IND",0,8,CHIP_UNSIGNED); + + /* RTF */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_RTF,"RTF",0xf439,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_RTF,FSTB0899_TIMING_LOOP_FREQ,"TIMING_LOOP_FREQ",0,8,CHIP_SIGNED); + + /* DSTATUS */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DSTATUS,"DSTATUS",0xf43a,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_DSTATUS,FSTB0899_CARRIER_FOUND,"CARRIER_FOUND",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DSTATUS,FSTB0899_TMG_LOCK,"TMG_LOCK",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DSTATUS,FSTB0899_LOCKED_FOR_DEM,"LOCKED_FOR_DEM",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DSTATUS,FSTB0899_TMG_AUTOSRCH_ON,"TMG_AUTOSRCH_ON",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DSTATUS,FSTB0899_END_MAINLOOP,"END_MAINLOOP",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DSTATUS,FSTB0899_DSTATUS_RESERVED,"DSTATUS_RESERVED",2,1,CHIP_UNSIGNED); + + /* LDI */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_LDI,"LDI",0xf43b,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_LDI,FSTB0899_LOCK_DET_INTEGR,"LOCK_DET_INTEGR",0,8,CHIP_SIGNED); + + /* CFRM */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_CFRM,"CFRM",0xf43e,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_CFRM,FSTB0899_CARRIER_FREQUENCY_MSB,"CARRIER_FREQUENCY_MSB",0,8,CHIP_SIGNED); + + /* CFRL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_CFRL,"CFRL",0xf43f,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_CFRL,FSTB0899_CARRIER_FREQUENCY_LSB,"CARRIER_FREQUENCY_LSB",0,8,CHIP_SIGNED); + + /* NIRM */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_NIRM,"NIRM",0xf440,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_NIRM,FSTB0899_NOISE_IND_MSB,"NOISE_IND_MSB",0,8,CHIP_UNSIGNED); + + /* NIRL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_NIRL,"NIRL",0xf441,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_NIRL,FSTB0899_NOISE_IND_LSB,"NOISE_IND_LSB",0,8,CHIP_UNSIGNED); + + /* ISYMB */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_ISYMB,"ISYMB",0xf444,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_ISYMB,FSTB0899_I_SYMBOL,"I_SYMBOL",0,8,CHIP_SIGNED); + + /* QSYMB */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_QSYMB,"QSYMB",0xf445,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_QSYMB,FSTB0899_Q_SYMBOL,"Q_SYMBOL",0,8,CHIP_SIGNED); + + /* SFRH */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_SFRH,"SFRH",0xf446,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_SFRH,FSTB0899_SYMB_FREQ_HSB,"SYMB_FREQ_HSB",0,8,CHIP_UNSIGNED); + + /* SFRM */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_SFRM,"SFRM",0xf447,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_SFRM,FSTB0899_SYMB_FREQ_MSB,"SYMB_FREQ_MSB",0,8,CHIP_UNSIGNED); + + /* SFRL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_SFRL,"SFRL",0xf448,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_SFRL,FSTB0899_SYMB_FREQ_LSB,"SYMB_FREQ_LSB",4,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_SFRL,FSTB0899_SFRL_RESERVED,"SFRL_RESERVED",0,4,CHIP_UNSIGNED); + + /* SFRUPH */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_SFRUPH,"SFRUPH",0xf44c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_SFRUPH,FSTB0899_SYMB_FREQ_UP_HSB,"SYMB_FREQ_UP_HSB",0,8,CHIP_UNSIGNED); + + /* SFRUPM */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_SFRUPM,"SFRUPM",0xf44d,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_SFRUPM,FSTB0899_SYMB_FREQ_UP_MSB,"SYMB_FREQ_UP_MSB",0,8,CHIP_UNSIGNED); + + /* SFRUPL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_SFRUPL,"SFRUPL",0xf44e,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_SFRUPL,FSTB0899_SYMB_FREQ_UP_LSB,"SYMB_FREQ_UP_LSB",4,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_SFRUPL,FSTB0899_SFRUPL_RESERVED,"SFRUPL_RESERVED",0,4,CHIP_UNSIGNED); + + /* EQUAI1 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_EQUAI1,"EQUAI1",0xf4e0,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_EQUAI1,FSTB0899_EQUAI1,"EQUAI1",0,8,CHIP_UNSIGNED); + + /* EQUAQ1 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_EQUAQ1,"EQUAQ1",0xf4e1,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_EQUAQ1,FSTB0899_EQUAQ1,"EQUAQ1",0,8,CHIP_UNSIGNED); + + /* EQUAI2 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_EQUAI2,"EQUAI2",0xf4e2,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_EQUAI2,FSTB0899_EQUAI2,"EQUAI2",0,8,CHIP_UNSIGNED); + + /* EQUAQ2 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_EQUAQ2,"EQUAQ2",0xf4e3,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_EQUAQ2,FSTB0899_EQUAQ2,"EQUAQ2",0,8,CHIP_UNSIGNED); + + /* EQUAI3 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_EQUAI3,"EQUAI3",0xf4e4,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_EQUAI3,FSTB0899_EQUAI3,"EQUAI3",0,8,CHIP_UNSIGNED); + + /* EQUAQ3 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_EQUAQ3,"EQUAQ3",0xf4e5,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_EQUAQ3,FSTB0899_EQUAQ3,"EQUAQ3",0,8,CHIP_UNSIGNED); + + /* EQUAI4 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_EQUAI4,"EQUAI4",0xf4e6,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_EQUAI4,FSTB0899_EQUAI4,"EQUAI4",0,8,CHIP_UNSIGNED); + + /* EQUAQ4 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_EQUAQ4,"EQUAQ4",0xf4e7,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_EQUAQ4,FSTB0899_EQUAQ4,"EQUAQ4",0,8,CHIP_UNSIGNED); + + /* EQUAI5 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_EQUAI5,"EQUAI5",0xf4e8,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_EQUAI5,FSTB0899_EQUAI5,"EQUAI5",0,8,CHIP_UNSIGNED); + + /* EQUAQ5 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_EQUAQ5,"EQUAQ5",0xf4e9,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_EQUAQ5,FSTB0899_EQUAQ5,"EQUAQ5",0,8,CHIP_UNSIGNED); + + /* DSTATUS2 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DSTATUS2,"DSTATUS2",0xf50c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_DSTATUS2,FSTB0899_DS2_TMGAUTOSRCH_ON,"DS2_TMGAUTOSRCH_ON",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DSTATUS2,FSTB0899_DS2_ENDMAINLOOP,"DS2_ENDMAINLOOP",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DSTATUS2,FSTB0899_DS2_CFSYNC,"DS2_CFSYNC",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DSTATUS2,FSTB0899_DS2_TMGLOCK,"DS2_TMGLOCK",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DSTATUS2,FSTB0899_DS2_DEMODWAIT,"DS2_DEMODWAIT",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DSTATUS2,FSTB0899_DSTATUS2_RESERVED,"DSTATUS2_RESERVED",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DSTATUS2,FSTB0899_DS2_FECON,"DS2_FECON",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DSTATUS2,FSTB0899_DSTATUS2_RESERVED2,"DSTATUS2_RESERVED2",0,1,CHIP_UNSIGNED); + + /* VSTATUS */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_VSTATUS,"VSTATUS",0xf50d,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_VSTATUS,FSTB0899_VITERBI_ON,"VITERBI_ON",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_VSTATUS,FSTB0899_END_LOOPVIT,"END_LOOPVIT",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_VSTATUS,FSTB0899_VSTATUS_RESERVED,"VSTATUS_RESERVED",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_VSTATUS,FSTB0899_PRFVIT,"PRFVIT",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_VSTATUS,FSTB0899_LOCKEDVIT,"LOCKEDVIT",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_VSTATUS,FSTB0899_VSTATUS_RESERVED2,"VSTATUS_RESERVED2",2,1,CHIP_UNSIGNED); + + /* VERROR */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_VERROR,"VERROR",0xf50f,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_VERROR,FSTB0899_ERROR_VAL,"ERROR_VAL",0,8,CHIP_UNSIGNED); + + /* IQSWAP */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_IQSWAP,"IQSWAP",0xf523,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_IQSWAP,FSTB0899_IQSWAP_RESERVED,"IQSWAP_RESERVED",4,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IQSWAP,FSTB0899_SYM,"SYM",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_IQSWAP,FSTB0899_IQSWAP_RESERVED2,"IQSWAP_RESERVED2",0,3,CHIP_UNSIGNED); + + /* ECNTM */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_ECNTM,"ECNTM",0xf524,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_ECNTM,FSTB0899_ERROR_COUNT_MSB,"ERROR_COUNT_MSB",0,8,CHIP_UNSIGNED); + + /* ECNTL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_ECNTL,"ECNTL",0xf525,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_ECNTL,FSTB0899_ERROR_COUNT_LSB,"ERROR_COUNT_LSB",0,8,CHIP_UNSIGNED); + + /* ECNT2M */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_ECNT2M,"ECNT2M",0xf526,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_ECNT2M,FSTB0899_ERROR_COUNT2_MSB,"ERROR_COUNT2_MSB",0,8,CHIP_UNSIGNED); + + /* ECNT2L */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_ECNT2L,"ECNT2L",0xf527,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_ECNT2L,FSTB0899_ERROR_COUNT2_LSB,"ERROR_COUNT2_LSB",0,8,CHIP_UNSIGNED); + + /* ECNT3M */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_ECNT3M,"ECNT3M",0xf528,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_ECNT3M,FSTB0899_ERROR_COUNT3_MSB,"ERROR_COUNT3_MSB",0,8,CHIP_UNSIGNED); + + /* ECNT3L */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_ECNT3L,"ECNT3L",0xf529,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_ECNT3L,FSTB0899_ERROR_COUNT3_LSB,"ERROR_COUNT3_LSB",0,8,CHIP_UNSIGNED); + + /* FECAUTO1 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_FECAUTO1,"FECAUTO1",0xf530,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_FECAUTO1,FSTB0899_FECAUTO1_RESERVED,"FECAUTO1_RESERVED",4,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_FECAUTO1,FSTB0899_FECAUTO1_RESERVED2,"FECAUTO1_RESERVED2",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_FECAUTO1,FSTB0899_SYMSRCH,"SYMSRCH",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_FECAUTO1,FSTB0899_QPSKSRCH,"QPSKSRCH",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_FECAUTO1,FSTB0899_BPSKSRCH,"BPSKSRCH",0,1,CHIP_UNSIGNED); + + /* FECM */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_FECM,"FECM",0xf533,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_FECM,FSTB0899_FECM_RESERVED0,"FECM_RESERVED0",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_FECM,FSTB0899_FECM_RESERVED,"FECM_RESERVED",4,3,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_FECM,FSTB0899_VITON,"VITON",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_FECM,FSTB0899_FECM_RESERVED2,"FECM_RESERVED2",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_FECM,FSTB0899_SYNCDIS,"SYNCDIS",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_FECM,FSTB0899_SYMI,"SYMI",0,1,CHIP_UNSIGNED); + + /* VTH12 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_VTH12,"VTH12",0xf534,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_VTH12,FSTB0899_VTH12,"VTH12",0,8,CHIP_UNSIGNED); + + /* VTH23 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_VTH23,"VTH23",0xf535,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_VTH23,FSTB0899_VTH23,"VTH23",0,8,CHIP_UNSIGNED); + + /* VTH34 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_VTH34,"VTH34",0xf536,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_VTH34,FSTB0899_VTH34,"VTH34",0,8,CHIP_UNSIGNED); + + /* VTH56 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_VTH56,"VTH56",0xf537,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_VTH56,FSTB0899_VTH56,"VTH56",0,8,CHIP_UNSIGNED); + + /* VTH67 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_VTH67,"VTH67",0xf538,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_VTH67,FSTB0899_VTH67,"VTH67",0,8,CHIP_UNSIGNED); + + /* VTH78 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_VTH78,"VTH78",0xf539,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_VTH78,FSTB0899_VTH78,"VTH78",0,8,CHIP_UNSIGNED); + + /* PRVIT */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_PRVIT,"PRVIT",0xf53c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_PRVIT,FSTB0899_PRVIT_RESERVED,"PRVIT_RESERVED",6,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_PRVIT,FSTB0899_PR_7_8,"PR_7_8",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_PRVIT,FSTB0899_PR_6_7,"PR_6_7",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_PRVIT,FSTB0899_PR_5_6,"PR_5_6",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_PRVIT,FSTB0899_PR_3_4,"PR_3_4",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_PRVIT,FSTB0899_PR_2_3,"PR_2_3",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_PRVIT,FSTB0899_PR_1_2,"PR_1_2",0,1,CHIP_UNSIGNED); + + /* VITSYNC */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_VITSYNC,"VITSYNC",0xf53d,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_VITSYNC,FSTB0899_AM,"AM",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_VITSYNC,FSTB0899_FREEZE,"FREEZE",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_VITSYNC,FSTB0899_SN,"SN",4,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_VITSYNC,FSTB0899_TO,"TO",2,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_VITSYNC,FSTB0899_HYST,"HYST",0,2,CHIP_UNSIGNED); + + /* RSULC */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_RSULC,"RSULC",0xf548,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_RSULC,FSTB0899_ULDIL_ON,"ULDIL_ON",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_RSULC,FSTB0899_ULAUTO_ON,"ULAUTO_ON",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_RSULC,FSTB0899_ULRS_ON,"ULRS_ON",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_RSULC,FSTB0899_ULDESCRAMB_ON,"ULDESCRAMB_ON",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_RSULC,FSTB0899_RSULC_RESERVED,"RSULC_RESERVED",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_RSULC,FSTB0899_UL_DISABLE,"UL_DISABLE",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_RSULC,FSTB0899_RSULC_RESERVED2,"RSULC_RESERVED2",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_RSULC,FSTB0899_UL_NOFTHRESHOLD,"UL_NOFTHRESHOLD",0,1,CHIP_UNSIGNED); + + /* TSULC */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSULC,"TSULC",0xf549,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSULC,FSTB0899_ULNOSYNCBYTES,"ULNOSYNCBYTES",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSULC,FSTB0899_ULPARYTY_ON,"ULPARYTY_ON",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSULC,FSTB0899_ULSYNCOUTRS,"ULSYNCOUTRS",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSULC,FSTB0899_TSULL_RESERVED,"TSULL_RESERVED",1,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSULC,FSTB0899_TSULL_RESERVED2,"TSULL_RESERVED2",0,1,CHIP_UNSIGNED); + + /* RSLLC */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_RSLLC,"RSLLC",0xf54a,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_RSLLC,FSTB0899_LLDIL_ON,"LLDIL_ON",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_RSLLC,FSTB0899_LLAUTO_ON,"LLAUTO_ON",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_RSLLC,FSTB0899_LLRS_ON,"LLRS_ON",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_RSLLC,FSTB0899_LLDESCRAMB_ON,"LLDESCRAMB_ON",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_RSLLC,FSTB0899_RSLLC_RESERVED,"RSLLC_RESERVED",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_RSLLC,FSTB0899_LL_DISABLE,"LL_DISABLE",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_RSLLC,FSTB0899_RSLLC_RESERVED2,"RSLLC_RESERVED2",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_RSLLC,FSTB0899_LL_NOFTHRESHOLD,"LL_NOFTHRESHOLD",0,1,CHIP_UNSIGNED); + + /* TSLPL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSLPL,"TSLPL",0xf54b,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSLPL,FSTB0899_TSLLL_RESERVED,"TSLLL_RESERVED",5,3,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSLPL,FSTB0899_LLDVBS2_MODE,"LLDVBS2_MODE",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSLPL,FSTB0899_LLISSYI_ON,"LLISSYI_ON",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSLPL,FSTB0899_LLNPD_ON,"LLNPD_ON",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSLPL,FSTB0899_LLCRC8_ON,"LLCRC8_ON",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSLPL,FSTB0899_TSLLL_RESERVED2,"TSLLL_RESERVED2",0,1,CHIP_UNSIGNED); + + /* TSCFGH */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSCFGH,"TSCFGH",0xf54c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSCFGH,FSTB0899_RSCFGH_RESERVED,"RSCFGH_RESERVED",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSCFGH,FSTB0899_OUTRS_PS,"OUTRS_PS",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSCFGH,FSTB0899_SYNCBYTE,"SYNCBYTE",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSCFGH,FSTB0899_PFBIT,"PFBIT",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSCFGH,FSTB0899_ERR_BIT,"ERR_BIT",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSCFGH,FSTB0899_MPEG,"MPEG",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSCFGH,FSTB0899_CLK_POL,"CLK_POL",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSCFGH,FSTB0899_FORCE0,"FORCE0",0,1,CHIP_UNSIGNED); + + /* TSCFGM */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSCFGM,"TSCFGM",0xf54d,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSCFGM,FSTB0899_RSCFGM_RESERVED,"RSCFGM_RESERVED",4,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSCFGM,FSTB0899_LLPRIORITY,"LLPRIORITY",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSCFGM,FSTB0899_EN_188,"EN_188",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSCFGM,FSTB0899_RSCFGM_RESERVED2,"RSCFGM_RESERVED2",0,2,CHIP_UNSIGNED); + + /* TSCFGL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSCFGL,"TSCFGL",0xf54e,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSCFGL,FSTB0899_DEL_ERRPACK,"DEL_ERRPACK",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSCFGL,FSTB0899_RSCFGL_RESERVED,"RSCFGL_RESERVED",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSCFGL,FSTB0899_ERRFLAGSTD,"ERRFLAGSTD",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSCFGL,FSTB0899_MPEGERR,"MPEGERR",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSCFGL,FSTB0899_BCH_CHK,"BCH_CHK",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSCFGL,FSTB0899_CRC8_CHK,"CRC8_CHK",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSCFGL,FSTB0899_ERRFLAG_MODE,"ERRFLAG_MODE",0,2,CHIP_UNSIGNED); + + /* TSOUT */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSOUT,"TSOUT",0xf54f,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSOUT,FSTB0899_OV_TSFIFO,"OV_TSFIFO",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSOUT,FSTB0899_ENA_AUTO,"ENA_AUTO",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSOUT,FSTB0899_EN_STBACKEND,"EN_STBACKEND",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSOUT,FSTB0899_ENA_LEVEL,"ENA_LEVEL",1,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSOUT,FSTB0899_ENA_FRAC,"ENA_FRAC",0,1,CHIP_UNSIGNED); + + /* RSSYNC */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_RSSYNC,"RSSYNC",0xf550,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_RSSYNC,FSTB0899_RST_DIL,"RST_DIL",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_RSSYNC,FSTB0899_RSISCR_DISABLE,"RSISCR_DISABLE",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_RSSYNC,FSTB0899_NPDREGEN_OFF,"NPDREGEN_OFF",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_RSSYNC,FSTB0899_RSPACKSYNC_DIS,"RSPACKSYNC_DIS",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_RSSYNC,FSTB0899_RSEXT_OUTENABLE,"RSEXT_OUTENABLE",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_RSSYNC,FSTB0899_RSSYNC_SEL,"RSSYNC_SEL",0,3,CHIP_UNSIGNED); + + /* TSINSDELH */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSINSDELH,"TSINSDELH",0xf551,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSINSDELH,FSTB0899_TSDEL_SYNCBYTE,"TSDEL_SYNCBYTE",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSINSDELH,FSTB0899_TSDEL_XXHEADER,"TSDEL_XXHEADER",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSINSDELH,FSTB0899_TSINS_LMTIMESTAM,"TSINS_LMTIMESTAM",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSINSDELH,FSTB0899_TSDEL_DATAFIELD,"TSDEL_DATAFIELD",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSINSDELH,FSTB0899_TSINS_ISCR,"TSINS_ISCR",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSINSDELH,FSTB0899_TSINS_NPD,"TSINS_NPD",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSINSDELH,FSTB0899_TSINS_RSPARITY,"TSINS_RSPARITY",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSINSDELH,FSTB0899_TSINS_CRC8,"TSINS_CRC8",0,1,CHIP_UNSIGNED); + + /* TSINSDELM */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSINSDELM,"TSINSDELM",0xf552,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSINSDELM,FSTB0899_TSDEL_BBPADDING,"TSDEL_BBPADDING",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSINSDELM,FSTB0899_TSDEL_BCHFEC,"TSDEL_BCHFEC",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSINSDELM,FSTB0899_TSDEL_LDPCFEC,"TSDEL_LDPCFEC",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSINSDELM,FSTB0899_TSINS_EMODCOD,"TSINS_EMODCOD",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSINSDELM,FSTB0899_TSINS_TOKEN,"TSINS_TOKEN",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSINSDELM,FSTB0899_TSINS_LDPCERR,"TSINS_LDPCERR",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSINSDELM,FSTB0899_TSINS_BCHERR,"TSINS_BCHERR",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSINSDELM,FSTB0899_TSINS_MATYPE,"TSINS_MATYPE",0,1,CHIP_UNSIGNED); + + /* TSINSDELL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSINSDELL,"TSINSDELL",0xf553,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSINSDELL,FSTB0899_TSINS_UPL,"TSINS_UPL",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSINSDELL,FSTB0899_TSINS_DFL,"TSINS_DFL",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSINSDELL,FSTB0899_TSINS_SYNC,"TSINS_SYNC",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSINSDELL,FSTB0899_TSINS_SYNCD,"TSINS_SYNCD",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSINSDELL,FSTB0899_TSINS_BLOCLEN,"TSINS_BLOCLEN",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSINSDELL,FSTB0899_TSINS_PCOUNT,"TSINS_PCOUNT",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSINSDELL,FSTB0899_TSINS_RSCONFIG,"TSINS_RSCONFIG",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSINSDELL,FSTB0899_TSINS_RSDIAG,"TSINS_RSDIAG",0,1,CHIP_UNSIGNED); + + /* TSLLSTKM */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSLLSTKM,"TSLLSTKM",0xf55a,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSLLSTKM,FSTB0899_DIL_FULL,"DIL_FULL",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSLLSTKM,FSTB0899_DILSTK_MSB,"DILSTK_MSB",0,7,CHIP_UNSIGNED); + + /* TSLLSTKL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSLLSTKL,"TSLLSTKL",0xf55b,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSLLSTKL,FSTB0899_DILSTK_LSB,"DILSTK_LSB",0,8,CHIP_UNSIGNED); + + /* TSULSTKM */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSULSTKM,"TSULSTKM",0xf55c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSULSTKM,FSTB0899_DILBW_FULL,"DILBW_FULL",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSULSTKM,FSTB0899_LOWP_EN,"LOWP_EN",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSULSTKM,FSTB0899_DIL_OVF,"DIL_OVF",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSULSTKM,FSTB0899_DILBWSTK_MSB,"DILBWSTK_MSB",0,5,CHIP_UNSIGNED); + + /* TSULSTKL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSULSTKL,"TSULSTKL",0xf55d,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSULSTKL,FSTB0899_DILBWSTK_LSB,"DILBWSTK_LSB",0,8,CHIP_UNSIGNED); + + /* PCKLENUL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_PCKLENUL,"PCKLENUL",0xf55e,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_PCKLENUL,FSTB0899_PACKET_LENGTH_UL,"PACKET_LENGTH_UL",0,8,CHIP_UNSIGNED); + + /* PCKLENLL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_PCKLENLL,"PCKLENLL",0xf55f,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_PCKLENLL,FSTB0899_PACKET_LENGTH_LL,"PACKET_LENGTH_LL",0,8,CHIP_UNSIGNED); + + /* RSPCKLEN */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_RSPCKLEN,"RSPCKLEN",0xf560,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_RSPCKLEN,FSTB0899_RS_PACKET_LENGTH,"RS_PACKET_LENGTH",0,8,CHIP_UNSIGNED); + + /* TSSTATUS */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSSTATUS,"TSSTATUS",0xf561,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSSTATUS,FSTB0899_LINE_OK,"LINE_OK",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSSTATUS,FSTB0899_ERROR,"ERROR",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSSTATUS,FSTB0899_LOW_PRIORITY,"LOW_PRIORITY",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSSTATUS,FSTB0899_DEC_DATA7,"DEC_DATA7",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSSTATUS,FSTB0899_RSOV_IN,"RSOV_IN",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSSTATUS,FSTB0899_ISCR_UPDATE,"ISCR_UPDATE",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSSTATUS,FSTB0899_TSSTATUS_RESERVED,"TSSTATUS_RESERVED",0,2,CHIP_UNSIGNED); + + /* ERRCTRL1 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_ERRCTRL1,"ERRCTRL1",0xf574,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_ERRCTRL1,FSTB0899_ERROR_SOURCE,"ERROR_SOURCE",3,5,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_ERRCTRL1,FSTB0899_NOE,"NOE",0,3,CHIP_UNSIGNED); + + /* ERRCTRL2 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_ERRCTRL2,"ERRCTRL2",0xf575,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_ERRCTRL2,FSTB0899_ERROR_SOURCE2,"ERROR_SOURCE2",3,5,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_ERRCTRL2,FSTB0899_NOE2,"NOE2",0,3,CHIP_UNSIGNED); + + /* ERRCTRL3 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_ERRCTRL3,"ERRCTRL3",0xf576,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_ERRCTRL3,FSTB0899_ERROR_SOURCE3,"ERROR_SOURCE3",3,5,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_ERRCTRL3,FSTB0899_NOE3,"NOE3",0,3,CHIP_UNSIGNED); + + /* DMONMSK1 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DMONMSK1,"DMONMSK1",0xf57b,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_DMONMSK1,FSTB0899_WAIT_1STEP,"WAIT_1STEP",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DMONMSK1,FSTB0899_FREE_14,"FREE_14",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DMONMSK1,FSTB0899_AVRGVIT_CALC,"AVRGVIT_CALC",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DMONMSK1,FSTB0899_FREE_12,"FREE_12",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DMONMSK1,FSTB0899_FREE_11,"FREE_11",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DMONMSK1,FSTB0899_B0DIV_CALC,"B0DIV_CALC",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DMONMSK1,FSTB0899_KDIVB1_CALC,"KDIVB1_CALC",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DMONMSK1,FSTB0899_KDIVB2_CALC,"KDIVB2_CALC",0,1,CHIP_UNSIGNED); + + /* DMONMSK0 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DMONMSK0,"DMONMSK0",0xf57c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_DMONMSK0,FSTB0899_SMOTTH_CALC,"SMOTTH_CALC",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DMONMSK0,FSTB0899_FREE_6,"FREE_6",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DMONMSK0,FSTB0899_SIGPOWER_CALC,"SIGPOWER_CALC",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DMONMSK0,FSTB0899_QSEUIL_CALC,"QSEUIL_CALC",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DMONMSK0,FSTB0899_FREE_3,"FREE_3",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DMONMSK0,FSTB0899_FREE_2,"FREE_2",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DMONMSK0,FSTB0899_KVDIVB1_CALC,"KVDIVB1_CALC",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DMONMSK0,FSTB0899_KVDIVB2_CLC,"KVDIVB2_CLC",0,1,CHIP_UNSIGNED); + + /* DEMAPVIT */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DEMAPVIT,"DEMAPVIT",0xf583,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_DEMAPVIT,FSTB0899_DEMAPVIT_RESERVED,"DEMAPVIT_RESERVED",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_DEMAPVIT,FSTB0899_KDIVIDER,"KDIVIDER",0,7,CHIP_UNSIGNED); + + /* PLPARM */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_PLPARM,"PLPARM",0xf58c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_PLPARM,FSTB0899_VIT_MAPPING,"VIT_MAPPING",5,3,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_PLPARM,FSTB0899_VIT_CURPUN,"VIT_CURPUN",0,5,CHIP_UNSIGNED); + + /* PDELCTRL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_PDELCTRL,"PDELCTRL",0xf600,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_PDELCTRL,FSTB0899_INVERTRES,"INVERTRES",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_PDELCTRL,FSTB0899_FORCEACCEPTED,"FORCEACCEPTED",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_PDELCTRL,FSTB0899_FILTEREN,"FILTEREN",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_PDELCTRL,FSTB0899_FSTLOCKFALLLOCKTHRESINC,"FSTLOCKFALLLOCKTHRESINC",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_PDELCTRL,FSTB0899_HYSTEN,"HYSTEN",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_PDELCTRL,FSTB0899_HYSTSWRST,"HYSTSWRST",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_PDELCTRL,FSTB0899_ALGOEN,"ALGOEN",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_PDELCTRL,FSTB0899_ALGOSWRST,"ALGOSWRST",0,1,CHIP_UNSIGNED); + + /* PDELCTRL2 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_PDELCTRL2,"PDELCTRL2",0xf601,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_PDELCTRL2,FSTB0899_FORCESYNC,"FORCESYNC",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_PDELCTRL2,FSTB0899_RSTUPKTKOCNT,"RSTUPKTKOCNT",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_PDELCTRL2,FSTB0899_RSTBBFKOCNT,"RSTBBFKOCNT",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_PDELCTRL2,FSTB0899_FORCELK,"FORCELK",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_PDELCTRL2,FSTB0899_DATASCRBLED,"DATASCRBLED",2,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_PDELCTRL2,FSTB0899_TSTYPERQST,"TSTYPERQST",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_PDELCTRL2,FSTB0899_SYNCDSUPDFL,"SYNCDSUPDFL",0,1,CHIP_UNSIGNED); + + /* BBHCTRL1 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_BBHCTRL1,"BBHCTRL1",0xf602,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_BBHCTRL1,FSTB0899_SYNCDSTREAM,"SYNCDSTREAM",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BBHCTRL1,FSTB0899_SYNCSTREAM,"SYNCSTREAM",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BBHCTRL1,FSTB0899_DFLSTREAM,"DFLSTREAM",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BBHCTRL1,FSTB0899_UPLSTREAM,"UPLSTREAM",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BBHCTRL1,FSTB0899_MATSTREAM,"MATSTREAM",0,1,CHIP_UNSIGNED); + + /* BBHCTRL2 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_BBHCTRL2,"BBHCTRL2",0xf603,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_BBHCTRL2,FSTB0899_SYNCDI2C,"SYNCDI2C",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BBHCTRL2,FSTB0899_SYNCI2C,"SYNCI2C",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BBHCTRL2,FSTB0899_DFLI2C,"DFLI2C",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BBHCTRL2,FSTB0899_UPLI2C,"UPLI2C",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BBHCTRL2,FSTB0899_MATI2C,"MATI2C",0,1,CHIP_UNSIGNED); + + /* HYSTTHRESH */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_HYSTTHRESH,"HYSTTHRESH",0xf604,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_HYSTTHRESH,FSTB0899_UNLOCK_THRESHOLD,"UNLOCK_THRESHOLD",4,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_HYSTTHRESH,FSTB0899_LOCKED_THRESHOLD,"LOCKED_THRESHOLD",0,4,CHIP_UNSIGNED); + + /* MATCSTM */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_MATCSTM,"MATCSTM",0xf605,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_MATCSTM,FSTB0899_MATCST_MSB,"MATCST_MSB",0,8,CHIP_UNSIGNED); + + /* MATCSTL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_MATCSTL,"MATCSTL",0xf606,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_MATCSTL,FSTB0899_MATCSTL_LSB,"MATCSTL_LSB",0,8,CHIP_UNSIGNED); + + /* UPLCSTM */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_UPLCSTM,"UPLCSTM",0xf607,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_UPLCSTM,FSTB0899_UPLCST_MSB,"UPLCST_MSB",0,8,CHIP_UNSIGNED); + + /* UPLCSTL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_UPLCSTL,"UPLCSTL",0xf608,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_UPLCSTL,FSTB0899_UPLCST_LSB,"UPLCST_LSB",0,8,CHIP_UNSIGNED); + + /* DFLCSTM */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DFLCSTM,"DFLCSTM",0xf609,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_DFLCSTM,FSTB0899_DFLCST_MSB,"DFLCST_MSB",0,8,CHIP_UNSIGNED); + + /* DFLCSTL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DFLCSTL,"DFLCSTL",0xf60a,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_DFLCSTL,FSTB0899_DFLCST_LSB,"DFLCST_LSB",0,8,CHIP_UNSIGNED); + + /* SYNCCST */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_SYNCCST,"SYNCCST",0xf60b,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_SYNCCST,FSTB0899_SYNC_CST,"SYNC_CST",0,8,CHIP_UNSIGNED); + + /* SYNCDCSTM */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_SYNCDCSTM,"SYNCDCSTM",0xf60c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_SYNCDCSTM,FSTB0899_SYNCDCST_MSB,"SYNCDCST_MSB",0,8,CHIP_UNSIGNED); + + /* SYNCDCSTL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_SYNCDCSTL,"SYNCDCSTL",0xf60d,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_SYNCDCSTL,FSTB0899_SYNCDCST_LSB,"SYNCDCST_LSB",0,8,CHIP_UNSIGNED); + + /* ISIENTRY */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_ISIENTRY,"ISIENTRY",0xf60e,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_ISIENTRY,FSTB0899_ISI_ENTRY,"ISI_ENTRY",0,8,CHIP_UNSIGNED); + + /* ISIBITEN */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_ISIBITEN,"ISIBITEN",0xf60f,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_ISIBITEN,FSTB0899_ISI_BIT_EN,"ISI_BIT_EN",0,8,CHIP_UNSIGNED); + + /* MATSTRM */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_MATSTRM,"MATSTRM",0xf610,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_MATSTRM,FSTB0899_MATSTR_MSB,"MATSTR_MSB",0,8,CHIP_UNSIGNED); + + /* MATSTRL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_MATSTRL,"MATSTRL",0xf611,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_MATSTRL,FSTB0899_MATSTR_LSB,"MATSTR_LSB",0,8,CHIP_UNSIGNED); + + /* UPLSTRM */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_UPLSTRM,"UPLSTRM",0xf612,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_UPLSTRM,FSTB0899_UPLSTR_MSB,"UPLSTR_MSB",0,8,CHIP_UNSIGNED); + + /* UPLSTRL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_UPLSTRL,"UPLSTRL",0xf613,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_UPLSTRL,FSTB0899_UPLSTR_LSB,"UPLSTR_LSB",0,8,CHIP_UNSIGNED); + + /* DFLSTRM */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DFLSTRM,"DFLSTRM",0xf614,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_DFLSTRM,FSTB0899_DFLSTR_MSB,"DFLSTR_MSB",0,8,CHIP_UNSIGNED); + + /* DFLSTRL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_DFLSTRL,"DFLSTRL",0xf615,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_DFLSTRL,FSTB0899_DFLSTR_LSB,"DFLSTR_LSB",0,8,CHIP_UNSIGNED); + + /* SYNCSTR */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_SYNCSTR,"SYNCSTR",0xf616,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_SYNCSTR,FSTB0899_SYNC_STR,"SYNC_STR",0,8,CHIP_UNSIGNED); + + /* SYNCDSTRM */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_SYNCDSTRM,"SYNCDSTRM",0xf617,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_SYNCDSTRM,FSTB0899_SYNCDSTR_MSB,"SYNCDSTR_MSB",0,8,CHIP_UNSIGNED); + + /* SYNCDSTRL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_SYNCDSTRL,"SYNCDSTRL",0xf618,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_SYNCDSTRL,FSTB0899_SYNCDSTR_LSB,"SYNCDSTR_LSB",0,8,CHIP_UNSIGNED); + + /* CFGPDELSTATUS1 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_CFGPDELSTATUS1,"CFGPDELSTATUS1",0xf619,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_CFGPDELSTATUS1,FSTB0899_CFGPDELSTATUS1_RESERVED,"CFGPDELSTATUS1_RESERVED",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CFGPDELSTATUS1,FSTB0899_BADDFL,"BADDFL",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CFGPDELSTATUS1,FSTB0899_CONTINUOUS_STREAM,"CONTINUOUS_STREAM",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CFGPDELSTATUS1,FSTB0899_ACCEPTED_STREAM,"ACCEPTED_STREAM",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CFGPDELSTATUS1,FSTB0899_BCH_ERROR_FLAG,"BCH_ERROR_FLAG",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CFGPDELSTATUS1,FSTB0899_CRCKO,"CRCKO",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CFGPDELSTATUS1,FSTB0899_LOCK,"LOCK",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CFGPDELSTATUS1,FSTB0899_FST_LOCK,"FST_LOCK",0,1,CHIP_UNSIGNED); + + /* CFGPKTDELSTTS2 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_CFGPKTDELSTTS2,"CFGPKTDELSTTS2",0xf61a,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_CFGPKTDELSTTS2,FSTB0899_FRAME_TYPE,"FRAME_TYPE",5,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CFGPKTDELSTTS2,FSTB0899_PACKET_DELIN_MODECODE,"PACKET_DELIN_MODECODE",0,5,CHIP_UNSIGNED); + + /* BBFERRORM */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_BBFERRORM,"BBFERRORM",0xf61b,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_BBFERRORM,FSTB0899_BBFCRCKOHCNT_MSB,"BBFCRCKOHCNT_MSB",0,8,CHIP_UNSIGNED); + + /* BBFERRORL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_BBFERRORL,"BBFERRORL",0xf61c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_BBFERRORL,FSTB0899_BBFCRCKOLCNT_LSB,"BBFCRCKOLCNT_LSB",0,8,CHIP_UNSIGNED); + + /* UPKTERRORM */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_UPKTERRORM,"UPKTERRORM",0xf61d,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_UPKTERRORM,FSTB0899_UPKTERROR_MSB,"UPKTERROR_MSB",0,8,CHIP_UNSIGNED); + + /* UPKTERRORL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_UPKTERRORL,"UPKTERRORL",0xf61e,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_UPKTERRORL,FSTB0899_UPKTERROR_LSB,"UPKTERROR_LSB",0,8,CHIP_UNSIGNED); + + /* BLOCKLNGTH */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_BLOCKLNGTH,"BLOCKLNGTH",0xfa04,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xfafc,0x0); + ChipAddField(hChip,RSTB0899_BLOCKLNGTH,FSTB0899_BLOCK_LENGTH,"BLOCK_LENGTH",0,8,CHIP_UNSIGNED); + + /* ROWSTR */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_ROWSTR,"ROWSTR",0xfa08,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xfafc,0x0); + ChipAddField(hChip,RSTB0899_ROWSTR,FSTB0899_ROW_STRIDE,"ROW_STRIDE",0,8,CHIP_UNSIGNED); + + /* MAXITER */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_MAXITER,"MAXITER",0xfa0c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xfafc,0x0); + ChipAddField(hChip,RSTB0899_MAXITER,FSTB0899_MAX_ITEARTIONS,"MAX_ITEARTIONS",0,8,CHIP_UNSIGNED); + + /* BNANDADDR */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_BNANDADDR,"BNANDADDR",0xfa10,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xfafc,0x0); + ChipAddField(hChip,RSTB0899_BNANDADDR,FSTB0899_BN_END_ADDR,"BN_END_ADDR",0,12,CHIP_UNSIGNED); + + /* CNANDADDR */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_CNANDADDR,"CNANDADDR",0xfa14,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xfafc,0x0); + ChipAddField(hChip,RSTB0899_CNANDADDR,FSTB0899_CN_END_ADDR,"CN_END_ADDR",0,12,CHIP_UNSIGNED); + + /* INFOLENGTH */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_INFOLENGTH,"INFOLENGTH",0xfa1c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xfafc,0x0); + ChipAddField(hChip,RSTB0899_INFOLENGTH,FSTB0899_INFO_LENGTH,"INFO_LENGTH",0,8,CHIP_UNSIGNED); + + /* BOT_ADDR */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_BOT_ADDR,"BOT_ADDR",0xfa20,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xfafc,0x0); + ChipAddField(hChip,RSTB0899_BOT_ADDR,FSTB0899_BOTTOM_BASE_ADDR,"BOTTOM_BASE_ADDR",0,10,CHIP_UNSIGNED); + + /* BCHBLKLN */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_BCHBLKLN,"BCHBLKLN",0xfa24,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xfafc,0x0); + ChipAddField(hChip,RSTB0899_BCHBLKLN,FSTB0899_BCH_BLOCK_LENGTH,"BCH_BLOCK_LENGTH",0,16,CHIP_UNSIGNED); + + /* BCHT */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_BCHT,"BCHT",0xfa28,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xfafc,0x0); + ChipAddField(hChip,RSTB0899_BCHT,FSTB0899_BCH_T,"BCH_T",0,4,CHIP_UNSIGNED); + + /* CNFGMODE */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_CNFGMODE,"CNFGMODE",0xfa00,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xfafc,0x800); + ChipAddField(hChip,RSTB0899_CNFGMODE,FSTB0899_MODCOD_REG,"MODCOD_REG",2,5,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CNFGMODE,FSTB0899_MODCOD_SEL,"MODCOD_SEL",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_CNFGMODE,FSTB0899_CONFIG_MODE,"CONFIG_MODE",0,1,CHIP_UNSIGNED); + + /* LDPCSTAT */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_LDPCSTAT,"LDPCSTAT",0xfa04,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xfafc,0x800); + ChipAddField(hChip,RSTB0899_LDPCSTAT,FSTB0899_ITERATION,"ITERATION",3,8,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_LDPCSTAT,FSTB0899_LDPC_DEC_STATE,"LDPC_DEC_STATE",0,3,CHIP_UNSIGNED); + + /* ITERSCALE */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_ITERSCALE,"ITERSCALE",0xfa08,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xfafc,0x800); + ChipAddField(hChip,RSTB0899_ITERSCALE,FSTB0899_ITERATION_SCALE,"ITERATION_SCALE",0,8,CHIP_UNSIGNED); + + /* INPUTMODE */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_INPUTMODE,"INPUTMODE",0xfa0c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xfafc,0x800); + ChipAddField(hChip,RSTB0899_INPUTMODE,FSTB0899_SD_BLOCK1_STREAM0,"SD_BLOCK1_STREAM0",0,1,CHIP_UNSIGNED); + + /* LDPCDECRST */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_LDPCDECRST,"LDPCDECRST",0xfa10,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xfafc,0x800); + ChipAddField(hChip,RSTB0899_LDPCDECRST,FSTB0899_LDPC_DEC_RST,"LDPC_DEC_RST",0,1,CHIP_UNSIGNED); + + /* CLKPERBYTE */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_CLKPERBYTE,"CLKPERBYTE",0xfa14,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xfafc,0x800); + ChipAddField(hChip,RSTB0899_CLKPERBYTE,FSTB0899_CLKS_PER_BYTE,"CLKS_PER_BYTE",0,5,CHIP_UNSIGNED); + + /* BCHERRORS */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_BCHERRORS,"BCHERRORS",0xfa18,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xfafc,0x800); + ChipAddField(hChip,RSTB0899_BCHERRORS,FSTB0899_BCH_ERRORS,"BCH_ERRORS",0,4,CHIP_UNSIGNED); + + /* LDPCERRORS */ + ChipAddReg(hChip,STCHIP_REG_16,RSTB0899_LDPCERRORS,"LDPCERRORS",0xfa1c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xfafc,0x800); + ChipAddField(hChip,RSTB0899_LDPCERRORS,FSTB0899_LDPC_ERRORS,"LDPC_ERRORS",0,16,CHIP_UNSIGNED); + + /* BCHMODE */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_BCHMODE,"BCHMODE",0xfa20,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xfafc,0x800); + ChipAddField(hChip,RSTB0899_BCHMODE,FSTB0899_FULL_BYPASS,"FULL_BYPASS",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_BCHMODE,FSTB0899_BCH_CORRECT_N,"BCH_CORRECT_N",0,1,CHIP_UNSIGNED); + + /* ERRACCPER */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_ERRACCPER,"ERRACCPER",0xfa24,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xfafc,0x800); + ChipAddField(hChip,RSTB0899_ERRACCPER,FSTB0899_BCH_ERR_ACCPERIOD,"BCH_ERR_ACCPERIOD",0,4,CHIP_UNSIGNED); + + /* BCHERRACC */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_BCHERRACC,"BCHERRACC",0xfa28,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xfafc,0x800); + ChipAddField(hChip,RSTB0899_BCHERRACC,FSTB0899_BCH_ERR_ACCUM,"BCH_ERR_ACCUM",0,8,CHIP_UNSIGNED); + + /* FECTPSEL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_FECTPSEL,"FECTPSEL",0xfa38,*DefVal++,STCHIP_ACCESS_WR,STCHIP_POINTED,0xfafc,0x800); + ChipAddField(hChip,RSTB0899_FECTPSEL,FSTB0899_FEC_TP_SEL,"FEC_TP_SEL",0,3,CHIP_UNSIGNED); + + /* TSTCK */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTCK,"TSTCK",0xff10,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTCK,FSTB0899_FORCETC,"FORCETC",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCK,FSTB0899_TSTCKRS,"TSTCKRS",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCK,FSTB0899_TSTCK_5,"TSTCK_5",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCK,FSTB0899_FORCEVIT,"FORCEVIT",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCK,FSTB0899_FORCEACS,"FORCEACS",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCK,FSTB0899_FORSYMHA,"FORSYMHA",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCK,FSTB0899_FORSYMAX,"FORSYMAX",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCK,FSTB0899_TSTCK_0,"TSTCK_0",0,1,CHIP_UNSIGNED); + + /* TSTRES */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTRES,"TSTRES",0xff11,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTRES,FSTB0899_FRESLDPC,"FRESLDPC",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRES,FSTB0899_FRESRS,"FRESRS",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRES,FSTB0899_FRESVIT,"FRESVIT",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRES,FSTB0899_FRESMAS1_2,"FRESMAS1_2",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRES,FSTB0899_FRESACS,"FRESACS",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRES,FSTB0899_FRESSYM,"FRESSYM",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRES,FSTB0899_FRESMAS,"FRESMAS",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRES,FSTB0899_FRESINT,"FRESINT",0,1,CHIP_UNSIGNED); + + /* TSTOUT */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTOUT,"TSTOUT",0xff12,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTOUT,FSTB0899_EN_SIGNATURE,"EN_SIGNATURE",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTOUT,FSTB0899_BCLK_CLOCK,"BCLK_CLOCK",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTOUT,FSTB0899_SGNL_OUT,"SGNL_OUT",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTOUT,FSTB0899_TS,"TS",1,4,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTOUT,FSTB0899_CTEST,"CTEST",0,1,CHIP_UNSIGNED); + + /* TSTIN */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTIN,"TSTIN",0xff13,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTIN,FSTB0899_TEST_IN,"TEST_IN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTIN,FSTB0899_EN_ADC,"EN_ADC",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTIN,FSTB0899_SGN_ADC,"SGN_ADC",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTIN,FSTB0899_BCLK_IN,"BCLK_IN",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTIN,FSTB0899_JETONIN_MODE,"JETONIN_MODE",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTIN,FSTB0899_BCLK_VALUE,"BCLK_VALUE",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTIN,FSTB0899_SGNRST_T12,"SGNRST_T12",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTIN,FSTB0899_LOWSP_ENAX,"LOWSP_ENAX",0,1,CHIP_UNSIGNED); + + /* TSTSYS */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTSYS,"TSTSYS",0xff14,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTSYS,FSTB0899_T11_ON_IOP21,"T11_ON_IOP21",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTSYS,FSTB0899_TSTSYS_6,"TSTSYS_6",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTSYS,FSTB0899_IP0_ENAX,"IP0_ENAX",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTSYS,FSTB0899_TC_BYPASS,"TC_BYPASS",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTSYS,FSTB0899_SYMRING_SAMPL,"SYMRING_SAMPL",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTSYS,FSTB0899_TBUSDOUPLOUT_MSK,"TBUSDOUPLOUT_MSK",1,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTSYS,FSTB0899_TST_CKSYNTHE,"TST_CKSYNTHE",0,1,CHIP_UNSIGNED); + + /* TSTCHIP */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTCHIP,"TSTCHIP",0xff15,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTCHIP,FSTB0899_TSTCHIP_7,"TSTCHIP_7",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCHIP,FSTB0899_INTBUF_BYPASS,"INTBUF_BYPASS",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCHIP,FSTB0899_DVBS2F_BYPASS,"DVBS2F_BYPASS",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCHIP,FSTB0899_TSTCHIP_4,"TSTCHIP_4",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCHIP,FSTB0899_TSTCHIP_3,"TSTCHIP_3",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCHIP,FSTB0899_TSTCHIP_2,"TSTCHIP_2",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCHIP,FSTB0899_LOWNOISE,"LOWNOISE",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCHIP,FSTB0899_STBY_ITER,"STBY_ITER",0,1,CHIP_UNSIGNED); + + /* TSTFREE */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTFREE,"TSTFREE",0xff16,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTFREE,FSTB0899_TSTFREE_7,"TSTFREE_7",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTFREE,FSTB0899_TSTFREE_6,"TSTFREE_6",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTFREE,FSTB0899_TSTFREE_5,"TSTFREE_5",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTFREE,FSTB0899_TSTFREE_4,"TSTFREE_4",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTFREE,FSTB0899_TSTFREE_3,"TSTFREE_3",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTFREE,FSTB0899_TSTFREE_2,"TSTFREE_2",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTFREE,FSTB0899_TSTFREE_1,"TSTFREE_1",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTFREE,FSTB0899_TSTFREE_0,"TSTFREE_0",0,1,CHIP_UNSIGNED); + + /* TSTI2C */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTI2C,"TSTI2C",0xff17,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTI2C,FSTB0899_EN_VI2C,"EN_VI2C",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTI2C,FSTB0899_TI2C,"TI2C",4,3,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTI2C,FSTB0899_TSTI2C_2,"TSTI2C_2",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTI2C,FSTB0899_DIS_I2CWAIT,"DIS_I2CWAIT",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTI2C,FSTB0899_I2C_FORCEACT,"I2C_FORCEACT",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTI2C,FSTB0899_TSTI2C_0,"TSTI2C_0",0,1,CHIP_UNSIGNED); + + /* BITSPEEDM */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_BITSPEEDM,"BITSPEEDM",0xff1c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_BITSPEEDM,FSTB0899_BITSPEED_MSB,"BITSPEED_MSB",0,8,CHIP_UNSIGNED); + + /* BITSPEEDL */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_BITSPEEDL,"BITSPEEDL",0xff1d,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_BITSPEEDL,FSTB0899_BITSPEED_LSB,"BITSPEED_LSB",0,8,CHIP_UNSIGNED); + + /* TBUSBIT */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TBUSBIT,"TBUSBIT",0xff1e,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TBUSBIT,FSTB0899_TBUSBIT_ENMODE,"TBUSBIT_ENMODE",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TBUSBIT,FSTB0899_TBUSBIT_SELECT,"TBUSBIT_SELECT",0,7,CHIP_UNSIGNED); + + /* TSTDIS */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTDIS,"TSTDIS",0xff24,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTDIS,FSTB0899_EN_DIS,"EN_DIS",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDIS,FSTB0899_EN_PTR,"EN_PTR",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDIS,FSTB0899_TSTDIS_EN_DISRX,"TSTDIS_EN_DISRX",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDIS,FSTB0899_TSTDIS_4,"TSTDIS_4",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDIS,FSTB0899_TSTDIS_3,"TSTDIS_3",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDIS,FSTB0899_TESTPRO,"TESTPRO",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDIS,FSTB0899_TESTREG,"TESTREG",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDIS,FSTB0899_TESTPRE,"TESTPRE",0,1,CHIP_UNSIGNED); + + /* TSTDISRX */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTDISRX,"TSTDISRX",0xff25,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTDISRX,FSTB0899_TSTDISRX_EN_DISRX,"TSTDISRX_EN_DISRX",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDISRX,FSTB0899_TST_CURRSRC,"TST_CURRSRC",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDISRX,FSTB0899_IN_DIGSIGNAL,"IN_DIGSIGNAL",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDISRX,FSTB0899_HIZ_CURRENTSRC,"HIZ_CURRENTSRC",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDISRX,FSTB0899_TSTDISRX_PIN_SELECT,"TSTDISRX_PIN_SELECT",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDISRX,FSTB0899_TST_DISRX,"TST_DISRX",0,3,CHIP_UNSIGNED); + + /* TSTJETON */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTJETON,"TSTJETON",0xff28,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTJETON,FSTB0899_TSTJETON_7,"TSTJETON_7",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTJETON,FSTB0899_TSTJETON_6,"TSTJETON_6",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTJETON,FSTB0899_TSTJETON_5,"TSTJETON_5",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTJETON,FSTB0899_TSTJETON_4,"TSTJETON_4",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTJETON,FSTB0899_TSTJETON_3,"TSTJETON_3",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTJETON,FSTB0899_TSTJETON_2,"TSTJETON_2",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTJETON,FSTB0899_TSTJETON_1,"TSTJETON_1",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTJETON,FSTB0899_TSTJETON_0,"TSTJETON_0",0,1,CHIP_UNSIGNED); + + /* TSTDCADJ */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTDCADJ,"TSTDCADJ",0xff40,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTDCADJ,FSTB0899_TSTDCADJ_7,"TSTDCADJ_7",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDCADJ,FSTB0899_TSTDCADJ_6,"TSTDCADJ_6",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDCADJ,FSTB0899_TST_DCADJ,"TST_DCADJ",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDCADJ,FSTB0899_ADJTST,"ADJTST",3,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDCADJ,FSTB0899_SEL_AVERAGE,"SEL_AVERAGE",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDCADJ,FSTB0899_DCADJ_Q,"DCADJ_Q",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDCADJ,FSTB0899_DCADJ_I,"DCADJ_I",0,1,CHIP_UNSIGNED); + + /* TSTAGC1 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTAGC1,"TSTAGC1",0xff41,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTAGC1,FSTB0899_EN_AGC1,"EN_AGC1",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTAGC1,FSTB0899_SEC_AGC1,"SEC_AGC1",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTAGC1,FSTB0899_EN_AGC1OUT,"EN_AGC1OUT",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTAGC1,FSTB0899_NAVERAGE_ON,"NAVERAGE_ON",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTAGC1,FSTB0899_EN_AGC1_MOD,"EN_AGC1_MOD",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTAGC1,FSTB0899_EN_AGC1_BETA,"EN_AGC1_BETA",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTAGC1,FSTB0899_EN_AGC1_PLF,"EN_AGC1_PLF",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTAGC1,FSTB0899_SEL_AGC1_TST,"SEL_AGC1_TST",0,1,CHIP_UNSIGNED); + + /* TSTAGC1N */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTAGC1N,"TSTAGC1N",0xff42,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTAGC1N,FSTB0899_EN_AGC1N,"EN_AGC1N",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTAGC1N,FSTB0899_AGC1N_PWM2,"AGC1N_PWM2",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTAGC1N,FSTB0899_AGC_BEF_DC,"AGC_BEF_DC",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTAGC1N,FSTB0899_AGC1N_PWM,"AGC1N_PWM",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTAGC1N,FSTB0899_EN_AGC1N_MOD,"EN_AGC1N_MOD",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTAGC1N,FSTB0899_EN_AGC1N_BETA,"EN_AGC1N_BETA",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTAGC1N,FSTB0899_EN_AGC1N_PLF,"EN_AGC1N_PLF",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTAGC1N,FSTB0899_SEL_AGC1N_TST,"SEL_AGC1N_TST",0,1,CHIP_UNSIGNED); + + /* TSTPOLYPH */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTPOLYPH,"TSTPOLYPH",0xff48,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTPOLYPH,FSTB0899_PPH_ITEST,"PPH_ITEST",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTPOLYPH,FSTB0899_PPH_QTEST,"PPH_QTEST",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTPOLYPH,FSTB0899_SEL_PPH,"SEL_PPH",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTPOLYPH,FSTB0899_SYMENA_BYP,"SYMENA_BYP",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTPOLYPH,FSTB0899_SEL_MULT,"SEL_MULT",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTPOLYPH,FSTB0899_EN_MULT,"EN_MULT",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTPOLYPH,FSTB0899_EN_BYPASS,"EN_BYPASS",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTPOLYPH,FSTB0899_SEL_CPT,"SEL_CPT",0,1,CHIP_UNSIGNED); + + /* TSTR */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTR,"TSTR",0xff49,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTR,FSTB0899_EN_STRTST,"EN_STRTST",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTR,FSTB0899_EN_RINGPOLY,"EN_RINGPOLY",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTR,FSTB0899_TSTR_5,"TSTR_5",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTR,FSTB0899_EN_FRAC,"EN_FRAC",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTR,FSTB0899_EN_STR_PLF,"EN_STR_PLF",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTR,FSTB0899_EN_STR_ERR,"EN_STR_ERR",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTR,FSTB0899_EN_STR_GPD,"EN_STR_GPD",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTR,FSTB0899_SEL_STR_TST,"SEL_STR_TST",0,1,CHIP_UNSIGNED); + + /* TSTAGC2 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTAGC2,"TSTAGC2",0xff4a,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTAGC2,FSTB0899_EN_AGC2,"EN_AGC2",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTAGC2,FSTB0899_TAGC2_6,"TAGC2_6",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTAGC2,FSTB0899_EN_AGC2M,"EN_AGC2M",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTAGC2,FSTB0899_EN_AGC2AC,"EN_AGC2AC",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTAGC2,FSTB0899_EN_AGC2_OUT,"EN_AGC2_OUT",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTAGC2,FSTB0899_TAGC2_2,"TAGC2_2",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTAGC2,FSTB0899_POLYPH_AMP,"POLYPH_AMP",0,2,CHIP_UNSIGNED); + + /* TSTCTL1 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTCTL1,"TSTCTL1",0xff4b,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTCTL1,FSTB0899_SEL_COR,"SEL_COR",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCTL1,FSTB0899_EN_CTL_NCO,"EN_CTL_NCO",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCTL1,FSTB0899_EN_CTL_PLF,"EN_CTL_PLF",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCTL1,FSTB0899_EN_CTL_CLM,"EN_CTL_CLM",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCTL1,FSTB0899_EN_CTL_DEROT,"EN_CTL_DEROT",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCTL1,FSTB0899_SEL_IQTHEORI,"SEL_IQTHEORI",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCTL1,FSTB0899_SEL_TETA,"SEL_TETA",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCTL1,FSTB0899_SEL_CTL_PLF,"SEL_CTL_PLF",0,1,CHIP_UNSIGNED); + + /* TSTCTL2 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTCTL2,"TSTCTL2",0xff4c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTCTL2,FSTB0899_EN_CTLTST,"EN_CTLTST",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCTL2,FSTB0899_EN_CTL_LOCIND,"EN_CTL_LOCIND",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCTL2,FSTB0899_EN_CLT_POLY,"EN_CLT_POLY",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCTL2,FSTB0899_EN_CTL_NOS,"EN_CTL_NOS",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCTL2,FSTB0899_EN_CTL_NOS_IND,"EN_CTL_NOS_IND",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCTL2,FSTB0899_EN_CTL_LOC_COS,"EN_CTL_LOC_COS",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCTL2,FSTB0899_TCTL2_1,"TCTL2_1",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCTL2,FSTB0899_TCTL2_0,"TCTL2_0",0,1,CHIP_UNSIGNED); + + /* TSTCTL3 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTCTL3,"TSTCTL3",0xff4d,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTCTL3,FSTB0899_TCTL3_7,"TCTL3_7",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCTL3,FSTB0899_TCTL3_6,"TCTL3_6",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCTL3,FSTB0899_TCTL3_5,"TCTL3_5",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCTL3,FSTB0899_TCTL3_4,"TCTL3_4",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCTL3,FSTB0899_TCTL3_3,"TCTL3_3",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCTL3,FSTB0899_TCTL3_2,"TCTL3_2",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCTL3,FSTB0899_TCTL3_1,"TCTL3_1",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTCTL3,FSTB0899_TCTL3_0,"TCTL3_0",0,1,CHIP_UNSIGNED); + + /* TSTDEMAP */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTDEMAP,"TSTDEMAP",0xff50,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTDEMAP,FSTB0899_EN_TBDEMAP,"EN_TBDEMAP",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDEMAP,FSTB0899_SMOT_RESTART,"SMOT_RESTART",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDEMAP,FSTB0899_SEL_ROTA,"SEL_ROTA",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDEMAP,FSTB0899_SEL_DATAIN,"SEL_DATAIN",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDEMAP,FSTB0899_NONZERO_ZI,"NONZERO_ZI",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDEMAP,FSTB0899_TDEMAP_MODE,"TDEMAP_MODE",0,3,CHIP_UNSIGNED); + + /* TSTDEMAP2 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTDEMAP2,"TSTDEMAP2",0xff51,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTDEMAP2,FSTB0899_XOR_HSBIT,"XOR_HSBIT",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDEMAP2,FSTB0899_TDEMAP2_6,"TDEMAP2_6",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDEMAP2,FSTB0899_N7PSK_TBL,"N7PSK_TBL",4,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDEMAP2,FSTB0899_TDEMAP2_3,"TDEMAP2_3",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDEMAP2,FSTB0899_TDEMAP2_2,"TDEMAP2_2",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDEMAP2,FSTB0899_TDEMAP2_1,"TDEMAP2_1",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDEMAP2,FSTB0899_TDEMAP2_0,"TDEMAP2_0",0,1,CHIP_UNSIGNED); + + /* TSTDEMMON */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTDEMMON,"TSTDEMMON",0xff52,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTDEMMON,FSTB0899_TDEMMON_7,"TDEMMON_7",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDEMMON,FSTB0899_TDEMMON_6,"TDEMMON_6",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDEMMON,FSTB0899_TDEMMON_5,"TDEMMON_5",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDEMMON,FSTB0899_TDEMMON_4,"TDEMMON_4",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDEMMON,FSTB0899_TDEMMON_3,"TDEMMON_3",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDEMMON,FSTB0899_TDEMMON_2,"TDEMMON_2",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDEMMON,FSTB0899_TDEMMON_1,"TDEMMON_1",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTDEMMON,FSTB0899_TDEMMON_0,"TDEMMON_0",0,1,CHIP_UNSIGNED); + + /* TSTRATE */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTRATE,"TSTRATE",0xff53,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTRATE,FSTB0899_FXPSK,"FXPSK",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRATE,FSTB0899_TSTRATE_6,"TSTRATE_6",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRATE,FSTB0899_TSTRATE_5,"TSTRATE_5",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRATE,FSTB0899_FSMOTLN,"FSMOTLN",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRATE,FSTB0899_FCURPUN,"FCURPUN",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRATE,FSTB0899_FTCPHASE,"FTCPHASE",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRATE,FSTB0899_FPHA,"FPHA",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRATE,FSTB0899_FROTA45,"FROTA45",0,1,CHIP_UNSIGNED); + + /* TSTSELOUT */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTSELOUT,"TSTSELOUT",0xff54,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTSELOUT,FSTB0899_EN_SYNC,"EN_SYNC",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTSELOUT,FSTB0899_SELOUT_5,"SELOUT_5",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTSELOUT,FSTB0899_TSTERR2,"TSTERR2",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTSELOUT,FSTB0899_TSTSYNCHRO_MODE,"TSTSYNCHRO_MODE",1,4,CHIP_UNSIGNED); + + /* TSYNC */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSYNC,"TSYNC",0xff55,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSYNC,FSTB0899_FCURPUNSYNC,"FCURPUNSYNC",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSYNC,FSTB0899_TSYNC_6,"TSYNC_6",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSYNC,FSTB0899_PRLOST_DELAY,"PRLOST_DELAY",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSYNC,FSTB0899_SRCH_ACCEL,"SRCH_ACCEL",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSYNC,FSTB0899_TSYNC_3,"TSYNC_3",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSYNC,FSTB0899_TSYNC_2,"TSYNC_2",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSYNC,FSTB0899_TST_BCHERRORLL,"TST_BCHERRORLL",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSYNC,FSTB0899_TST_BCHERRORUL,"TST_BCHERRORUL",0,1,CHIP_UNSIGNED); + + /* TSTERR */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTERR,"TSTERR",0xff56,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTERR,FSTB0899_TSTERR_7,"TSTERR_7",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTERR,FSTB0899_TSTERR_6,"TSTERR_6",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTERR,FSTB0899_TSTERR_5,"TSTERR_5",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTERR,FSTB0899_TSTERR_4,"TSTERR_4",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTERR,FSTB0899_TSTERR_3,"TSTERR_3",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTERR,FSTB0899_TSTERR_2,"TSTERR_2",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTERR,FSTB0899_FROTA45_FIRST,"FROTA45_FIRST",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTERR,FSTB0899_TSTERR_0,"TSTERR_0",0,1,CHIP_UNSIGNED); + + /* TSTRAM1 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTRAM1,"TSTRAM1",0xff58,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTRAM1,FSTB0899_SELADR1,"SELADR1",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRAM1,FSTB0899_FSELRAM1,"FSELRAM1",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRAM1,FSTB0899_FSELDEC,"FSELDEC",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRAM1,FSTB0899_FOEB,"FOEB",2,3,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRAM1,FSTB0899_FADR,"FADR",0,2,CHIP_UNSIGNED); + + /* TSTVSELOUT */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTVSELOUT,"TSTVSELOUT",0xff59,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTVSELOUT,FSTB0899_EN_VLOG,"EN_VLOG",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTVSELOUT,FSTB0899_VSELOUT_6,"VSELOUT_6",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTVSELOUT,FSTB0899_VSELOUT_5,"VSELOUT_5",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTVSELOUT,FSTB0899_VSELOUT_4,"VSELOUT_4",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTVSELOUT,FSTB0899_VSELOUT_3,"VSELOUT_3",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTVSELOUT,FSTB0899_SELLIFO,"SELLIFO",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTVSELOUT,FSTB0899_SELFIFO,"SELFIFO",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTVSELOUT,FSTB0899_VIT_DIFF,"VIT_DIFF",0,1,CHIP_UNSIGNED); + + /* TSTFORCEIN */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTFORCEIN,"TSTFORCEIN",0xff5a,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTFORCEIN,FSTB0899_SEL_VITDATAIN,"SEL_VITDATAIN",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTFORCEIN,FSTB0899_FORCE_ACS,"FORCE_ACS",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTFORCEIN,FSTB0899_FORCEIN_5,"FORCEIN_5",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTFORCEIN,FSTB0899_TSTRAM64,"TSTRAM64",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTFORCEIN,FSTB0899_TSTRAM,"TSTRAM",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTFORCEIN,FSTB0899_FORCEIN_2,"FORCEIN_2",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTFORCEIN,FSTB0899_TSTERRV,"TSTERRV",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTFORCEIN,FSTB0899_TSTACS,"TSTACS",0,1,CHIP_UNSIGNED); + + /* TSTRS1 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTRS1,"TSTRS1",0xff5c,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTRS1,FSTB0899_TSTSCRA,"TSTSCRA",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRS1,FSTB0899_OLDRS6,"OLDRS6",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRS1,FSTB0899_EN_SCRAMHYST,"EN_SCRAMHYST",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRS1,FSTB0899_LNB_TSTOUT,"LNB_TSTOUT",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRS1,FSTB0899_DILT,"DILT",2,2,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRS1,FSTB0899_TST_DILBW,"TST_DILBW",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRS1,FSTB0899_TSTRSEN,"TSTRSEN",0,1,CHIP_UNSIGNED); + + /* TSTRS2 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTRS2,"TSTRS2",0xff5d,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTRS2,FSTB0899_MOD_SYNCBYTE,"MOD_SYNCBYTE",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRS2,FSTB0899_DILFFULL_IGNORE,"DILFFULL_IGNORE",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRS2,FSTB0899_FORCE_ISCR3BYTES,"FORCE_ISCR3BYTES",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRS2,FSTB0899_TSTRS_SERIAL,"TSTRS_SERIAL",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRS2,FSTB0899_MMISDEC_ON,"MMISDEC_ON",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRS2,FSTB0899_TSERS3,"TSERS3",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRS2,FSTB0899_TSERS2,"TSERS2",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRS2,FSTB0899_TSERS,"TSERS",0,1,CHIP_UNSIGNED); + + /* TSTRS3 */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_TSTRS3,"TSTRS3",0xff5e,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_TSTRS3,FSTB0899_TSTRS3_7,"TSTRS3_7",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRS3,FSTB0899_TSTRS3_6,"TSTRS3_6",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRS3,FSTB0899_TSTRS3_5,"TSTRS3_5",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRS3,FSTB0899_TSTRS3_4,"TSTRS3_4",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRS3,FSTB0899_TSTRS3_3,"TSTRS3_3",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRS3,FSTB0899_TSTRS3_2,"TSTRS3_2",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRS3,FSTB0899_TSTRS3_1,"TSTRS3_1",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RSTB0899_TSTRS3,FSTB0899_DIL_DBBHEADER,"DIL_DBBHEADER",0,1,CHIP_UNSIGNED); + + /* GHOSTREG */ + ChipAddReg(hChip,STCHIP_REG_8,RSTB0899_GHOSTREG,"GHOSTREG",0xf000,*DefVal++,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0x0000,0x0); + ChipAddField(hChip,RSTB0899_GHOSTREG,FSTB0899_GHOSTFIELD,"GHOSTFIELD",0,7,CHIP_UNSIGNED); + + //printk(KERN_ERR "ChipApplyDefaultValues-->>\n"); + ChipApplyDefaultValues(hChip); + //printk(KERN_ERR "ChipApplyDefaultValues<<--\n"); + } + } + return hChip; +} + +STCHIP_Handle_t LNBP21_Init(STCHIP_Info_t *Chip) +{ + STCHIP_Handle_t hChip; + + /* fill elements of external chip data structure */ + Chip->NbRegs = LNBP21_NBREGS; + Chip->NbFields = LNBP21_NBFIELDS; + Chip->ChipMode = STCHIP_MODE_NOSUBADR; + Chip->WrStart = RLNBP21_SYSTEM; + Chip->WrSize = 1; + Chip->RdStart = RLNBP21_SYSTEM; + Chip->RdSize = 1; + + hChip = ChipOpen(Chip); + + if(hChip != NULL) + { + /* SYSTEM */ + ChipAddReg(hChip,STCHIP_REG_8,RLNBP21_SYSTEM,"SYSTEM",0x00,0x00,STCHIP_ACCESS_WR,STCHIP_NOT_POINTED,0,0); + ChipAddField(hChip,RLNBP21_SYSTEM,FLNBP21_PCL,"PCL",7,1,CHIP_UNSIGNED); + ChipAddField(hChip,RLNBP21_SYSTEM,FLNBP21_ISEL,"ISEL",6,1,CHIP_UNSIGNED); + ChipAddField(hChip,RLNBP21_SYSTEM,FLNBP21_TEN,"TEN",5,1,CHIP_UNSIGNED); + ChipAddField(hChip,RLNBP21_SYSTEM,FLNBP21_LLC,"LLC",4,1,CHIP_UNSIGNED); + ChipAddField(hChip,RLNBP21_SYSTEM,FLNBP21_VSEL,"VSEL",3,1,CHIP_UNSIGNED); + ChipAddField(hChip,RLNBP21_SYSTEM,FLNBP21_EN,"EN",2,1,CHIP_UNSIGNED); + ChipAddField(hChip,RLNBP21_SYSTEM,FLNBP21_OTF,"OTF",1,1,CHIP_UNSIGNED); + ChipAddField(hChip,RLNBP21_SYSTEM,FLNBP21_OLF,"OLF",0,1,CHIP_UNSIGNED); + } + + return hChip; +} + + diff -u -r -N -b kernel-2.6.24.4-orig/drivers/media/dvb/frontends/stb0899_init.h kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/stb0899_init.h --- kernel-2.6.24.4-orig/drivers/media/dvb/frontends/stb0899_init.h 1970-01-01 06:00:00.000000000 +0600 +++ kernel-2.6.24.4-twinhan/drivers/media/dvb/frontends/stb0899_init.h 2008-04-03 05:09:52.000000000 +0700 @@ -0,0 +1,2670 @@ +#ifndef STB0899_INIT_H +#define STB0899_INIT_H + +#include "stb0899_chip.h" +#include "stb0899_common.h" + +/* ID */ +#define RSTB0899_ID 0 +#define FSTB0899_CHIP_IDENT 0 +#define FSTB0899_RELEASE 1 + +/* TDISCNTRL1 */ +#define RSTB0899_TDISCNTRL1 1 +#define FSTB0899_TIMOFF 2 +#define FSTB0899_DISEQC_RESET 3 +#define FSTB0899_TIMCMD 4 +#define FSTB0899_TDISCNTRL1_RESERVED 5 +#define FSTB0899_DISPRECHARGE 6 +#define FSTB0899_DISEQCMODE 7 + +/* DISCNTRL2 */ +#define RSTB0899_DISCNTRL2 2 +#define FSTB0899_RECEIVER_ON 8 +#define FSTB0899_IGNO_SHORT22K 9 +#define FSTB0899_ONECHIPTRX 10 +#define FSTB0899_EXTENVELOP 11 +#define FSTB0899_PINSELECT 12 +#define FSTB0899_IRQRXEND 13 +#define FSTB0899_IRQ4NBYTES 14 + +/* DISRX_ST0 */ +#define RSTB0899_DISRX_ST0 3 +#define FSTB0899_RXEND 15 +#define FSTB0899_RXACTIVE 16 +#define FSTB0899_SHORT22K 17 +#define FSTB0899_CONTTONE 18 +#define FSTB0899_DIS_4BFIFORDY 19 +#define FSTB0899_FIFOEMPTY 20 +#define FSTB0899_DISRX_ST0_RESERVED 21 +#define FSTB0899_ABORTRX 22 + +/* DISRX_ST1 */ +#define RSTB0899_DISRX_ST1 4 +#define FSTB0899_RXFAIL 23 +#define FSTB0899_FIFOPFAIL 24 +#define FSTB0899_RXNONBYTE 25 +#define FSTB0899_FIFOOVF 26 +#define FSTB0899_FIFOBYTENBR 27 + +/* DISPARITY */ +#define RSTB0899_DISPARITY 5 +#define FSTB0899_DISEQC_PARITY 28 + +/* DISFIFO */ +#define RSTB0899_DISFIFO 6 +#define FSTB0899_DISEQCFIFO 29 + +/* DISSTATUS */ +#define RSTB0899_DISSTATUS 7 +#define FSTB0899_TXFAIL 30 +#define FSTB0899_FIFOPARITYFAIL 31 +#define FSTB0899_DISS_RXNONBYTE 32 +#define FSTB0899_GAPBURST 33 +#define FSTB0899_TXFIFOBYTES 34 + +/* DISF22 */ +#define RSTB0899_DISF22 8 +#define FSTB0899_F22 35 + +/* DISF22RX */ +#define RSTB0899_DISF22RX 9 +#define FSTB0899_F22RX 36 + +/* SYSREG */ +#define RSTB0899_SYSREG 10 +#define FSTB0899_SYS_MODE 37 +#define FSTB0899_DUPLMODE_IN 38 +#define FSTB0899_DUPLIN_3CK 39 +#define FSTB0899_DUPLMODE_OUT 40 +#define FSTB0899_SYSREG_1 41 +#define FSTB0899_RST_IQLSB_IN 42 + +/* ACRPRESC */ +#define RSTB0899_ACRPRESC 11 +#define FSTB0899_ACRPRESC_RESERVED 43 +#define FSTB0899_ACRPRESC 44 +#define FSTB0899_ACRPRESC_RESERVED2 45 +#define FSTB0899_ACRPRESC2 46 + +/* ACRDIV1 */ +#define RSTB0899_ACRDIV1 12 +#define FSTB0899_ACRDIV1 47 + +/* ACRDIV2 */ +#define RSTB0899_ACRDIV2 13 +#define FSTB0899_ACRDIV2 48 + +/* DACR1 */ +#define RSTB0899_DACR1 14 +#define FSTB0899_DACMODE 49 +#define FSTB0899_DACHZ 50 +#define FSTB0899_DAC_MSB 51 + +/* DACR2 */ +#define RSTB0899_DACR2 15 +#define FSTB0899_DAC_LSB 52 + +/* OUTCFG */ +#define RSTB0899_OUTCFG 16 +#define FSTB0899_TSSEROUTHZ 53 +#define FSTB0899_TSPOUTHZ 54 +#define FSTB0899_OUTCFG_RESERVED 55 + +/* MODECFG */ +#define RSTB0899_MODECFG 17 +#define FSTB0899_INV_DATA 56 +#define FSTB0899_INV_DATA6 57 +#define FSTB0899_MODECFG_RESERVED 58 +#define FSTB0899_INV_ERROR 59 +#define FSTB0899_INV_STROUT 60 +#define FSTB0899_INV_DP 61 + +/* IRQSTATUS3 */ +#define RSTB0899_IRQSTATUS3 18 +#define FSTB0899_SIP1 62 +#define FSTB0899_NSIP1 63 +#define FSTB0899_SCF_SYNC 64 +#define FSTB0899_NSCF_SYNC 65 +#define FSTB0899_SAGC0_LOCK 66 +#define FSTB0899_NSAGC0_LOCK 67 +#define FSTB0899_SDISEQCTX_IRQ 68 +#define FSTB0899_SDISEQCRX_IRQ 69 + +/* IRQSTATUS2 */ +#define RSTB0899_IRQSTATUS2 19 +#define FSTB0899_SEND_LOOPTC 70 +#define FSTB0899_SOV_RSFIFO 71 +#define FSTB0899_SLOCKEDBW 72 +#define FSTB0899_NSLOCKEDBW 73 +#define FSTB0899_SPRFBW 74 +#define FSTB0899_NSPRFBW 75 +#define FSTB0899_SINPUTX 76 +#define FSTB0899_NSINPUTX 77 + +/* IRQSTATUS1 */ +#define RSTB0899_IRQSTATUS1 20 +#define FSTB0899_SEND_LOOPVIT 78 +#define FSTB0899_SDMON_ELOOP 79 +#define FSTB0899_SLOCKED 80 +#define FSTB0899_NSLOCKED 81 +#define FSTB0899_SPRF 82 +#define FSTB0899_NSPRF 83 +#define FSTB0899_SSMOTIF_LOCKED 84 +#define FSTB0899_NSSMOTIF_LOCD 85 + +/* IRQSTATUS0 */ +#define RSTB0899_IRQSTATUS0 21 +#define FSTB0899_SFIFOFULL_CODIN 86 +#define FSTB0899_SCOD_NEAR_EMPTY 87 +#define FSTB0899_SCOD_FIFO_READY 88 +#define FSTB0899_SDECIN_OVER 89 +#define FSTB0899_SRSSYNC_OK 90 +#define FSTB0899_SLNBTX_IRQ 91 +#define FSTB0899_SSPY_ENDSIM 92 +#define FSTB0899_SSPY_VALIDSI 93 + +/* IRQMSK3 */ +#define RSTB0899_IRQMSK3 22 +#define FSTB0899_MIP1 94 +#define FSTB0899_NMIP1 95 +#define FSTB0899_MCF_SYNC 96 +#define FSTB0899_NMCF_SYNC 97 +#define FSTB0899_MAGC0_LOCK 98 +#define FSTB0899_NMAGC0_LOCK 99 +#define FSTB0899_MDISEQCTX_IRQ 100 +#define FSTB0899_MDISEQCRX_IRQ 101 + +/* IRQMSK2 */ +#define RSTB0899_IRQMSK2 23 +#define FSTB0899_MEND_LOOPTC 102 +#define FSTB0899_MOV_RSFIFO 103 +#define FSTB0899_MLOCKEDBW 104 +#define FSTB0899_NMLOCKEDBW 105 +#define FSTB0899_MPRFBW 106 +#define FSTB0899_NMPRFBW 107 +#define FSTB0899_MINPUTX 108 +#define FSTB0899_NMINPUTX 109 + +/* IRQMSK1 */ +#define RSTB0899_IRQMSK1 24 +#define FSTB0899_MEND_LOOPVIT 110 +#define FSTB0899_MDMON_ELOOP 111 +#define FSTB0899_MLOCKED 112 +#define FSTB0899_NMLOCKED 113 +#define FSTB0899_MPRF 114 +#define FSTB0899_NMPRF 115 +#define FSTB0899_MSMOTIF_LOCKED 116 +#define FSTB0899_NMSMOTIF_LOCD 117 + +/* IRQMSK0 */ +#define RSTB0899_IRQMSK0 25 +#define FSTB0899_NFIFOFULL_CODIN 118 +#define FSTB0899_NCOD_NEAR_EMPTY 119 +#define FSTB0899_MCOD_FIFO_READY 120 +#define FSTB0899_MDECIN_OVER 121 +#define FSTB0899_MRSSYNC_OK 122 +#define FSTB0899_MLNBTX_IRQ 123 +#define FSTB0899_MSPY_ENDSIM 124 +#define FSTB0899_MSPY_VALIDSI 125 + +/* IRQCFG */ +#define RSTB0899_IRQCFG 26 +#define FSTB0899_NINV_IRQ17 126 +#define FSTB0899_SEL_IRQ17 127 +#define FSTB0899_INV_IRQ16 128 +#define FSTB0899_SEL_IRQ16 129 + +/* I2CCFG */ +#define RSTB0899_I2CCFG 27 +#define FSTB0899_I2CCFG_RESERVED 130 +#define FSTB0899_I2CCFG_RESERVED2 131 +#define FSTB0899_I2CCFG_RESERVED3 132 +#define FSTB0899_I2CCFG_RESERVED4 133 +#define FSTB0899_I2CFASTMODE 134 +#define FSTB0899_STATUSWR 135 +#define FSTB0899_I2CADDRINC 136 + +/* I2CRPT */ +#define RSTB0899_I2CRPT 28 +#define FSTB0899_I2CTON 137 +#define FSTB0899_ENARPTLEVEL 138 +#define FSTB0899_SCLTDELAY 139 +#define FSTB0899_STOPENA 140 +#define FSTB0899_STOPSDAT2SDA 141 +#define FSTB0899_I2CRPT_RESERVED 142 + +/* IOPVALUE8 */ +#define RSTB0899_IOPVALUE8 29 +#define FSTB0899_VTIME_COHERENT 143 +#define FSTB0899_IOPVALUE8_6 144 +#define FSTB0899_IOPVALUE8_5 145 +#define FSTB0899_VIOP37 146 +#define FSTB0899_VIOP36 147 +#define FSTB0899_VIOP35 148 +#define FSTB0899_VIOP34 149 +#define FSTB0899_VIOP33 150 + +/* IOPVALUE7 */ +#define RSTB0899_IOPVALUE7 30 +#define FSTB0899_VIOP32 151 +#define FSTB0899_VIOP31 152 +#define FSTB0899_VIOP30 153 +#define FSTB0899_VIOP27 154 +#define FSTB0899_VIOP26 155 +#define FSTB0899_VIOP25 156 +#define FSTB0899_VIOP24 157 +#define FSTB0899_VIOP23 158 + +/* IOPVALUE6 */ +#define RSTB0899_IOPVALUE6 31 +#define FSTB0899_VIOP22 159 +#define FSTB0899_VIOP21 160 +#define FSTB0899_VIOP20 161 +#define FSTB0899_VIOP17 162 +#define FSTB0899_VIOP16 163 +#define FSTB0899_VIOP15 164 +#define FSTB0899_VIOP14 165 +#define FSTB0899_VIOP13 166 + +/* IOPVALUE5 */ +#define RSTB0899_IOPVALUE5 32 +#define FSTB0899_VIOP12 167 +#define FSTB0899_VIOP11 168 +#define FSTB0899_VIOP10 169 +#define FSTB0899_VPACKDP 170 +#define FSTB0899_VDEC_DATA6 171 +#define FSTB0899_VDEC_DATA5 172 +#define FSTB0899_VDEC_DATA4 173 +#define FSTB0899_VDEC_DATA3 174 + +/* IOPVALUE4 */ +#define RSTB0899_IOPVALUE4 33 +#define FSTB0899_VDEC_DATA2 175 +#define FSTB0899_VDEC_DATA1 176 +#define FSTB0899_VDEC_DATA0 177 +#define FSTB0899_VDISEQC_IN 178 +#define FSTB0899_VIP2 179 +#define FSTB0899_VIP1_4 180 +#define FSTB0899_VPACKSYNC_4 181 +#define FSTB0899_VSDAT 182 + +/* IOPVALUE3 */ +#define RSTB0899_IOPVALUE3 34 +#define FSTB0899_VIOP5_3 183 +#define FSTB0899_VIOP4 184 +#define FSTB0899_VSCLT 185 +#define FSTB0899_VAGCRF 186 +#define FSTB0899_VAGCQ 187 +#define FSTB0899_VAGCIQ 188 +#define FSTB0899_VSDA 189 +#define FSTB0899_VOP2 190 + +/* IOPVALUE2 */ +#define RSTB0899_IOPVALUE2 35 +#define FSTB0899_VOP1 191 +#define FSTB0899_VOP0 192 +#define FSTB0899_VERR_FLAG 193 +#define FSTB0899_VSYNC_CLK 194 +#define FSTB0899_VPACK_CLK 195 +#define FSTB0899_VDEC_DATA7 196 +#define FSTB0899_IOP4 197 +#define FSTB0899_BYTE_CLK 198 + +/* IOPVALUE1 */ +#define RSTB0899_IOPVALUE1 36 +#define FSTB0899_VDISEQC 199 +#define FSTB0899_VSCL 200 +#define FSTB0899_VAUX_CK 201 +#define FSTB0899_VDAC 202 +#define FSTB0899_VIP1_1 203 +#define FSTB0899_VIOP5_1 204 +#define FSTB0899_VATT 205 +#define FSTB0899_VT7_CS0 206 + +/* IOPVALUE0 */ +#define RSTB0899_IOPVALUE0 37 +#define FSTB0899_VT12_CS1 207 +#define FSTB0899_VT6_DIRCLK 208 +#define FSTB0899_VENAFIFOI 209 +#define FSTB0899_VPACKSYNC_0 210 +#define FSTB0899_VDATACK 211 +#define FSTB0899_VDATA7 212 +#define FSTB0899_VT1_STDBY 213 +#define FSTB0899_VIP0 214 + +/* GPIO0CFG */ +#define RSTB0899_GPIO0CFG 38 +#define FSTB0899_GPIO0_OPDRAIN 215 +#define FSTB0899_GPIO0_CONFIG 216 +#define FSTB0899_GPIO0_XOR 217 + +/* GPIO1CFG */ +#define RSTB0899_GPIO1CFG 39 +#define FSTB0899_GPIO1_OPDRAIN 218 +#define FSTB0899_GPIO1_CONFIG 219 +#define FSTB0899_GPIO1_XOR 220 + +/* GPIO2CFG */ +#define RSTB0899_GPIO2CFG 40 +#define FSTB0899_GPIO2_OPDRAIN 221 +#define FSTB0899_GPIO2_CONFIG 222 +#define FSTB0899_GPIO2_XOR 223 + +/* GPIO3CFG */ +#define RSTB0899_GPIO3CFG 41 +#define FSTB0899_GPIO3_OPDRAIN 224 +#define FSTB0899_GPIO3_CONFIG 225 +#define FSTB0899_GPIO3_XOR 226 + +/* GPIO4CFG */ +#define RSTB0899_GPIO4CFG 42 +#define FSTB0899_GPIO4_OPDRAIN 227 +#define FSTB0899_GPIO4_CONFIG 228 +#define FSTB0899_GPIO4_XOR 229 + +/* GPIO5CFG */ +#define RSTB0899_GPIO5CFG 43 +#define FSTB0899_GPIO5_OPDRAIN 230 +#define FSTB0899_GPIO5_CONFIG 231 +#define FSTB0899_GPIO5_XOR 232 + +/* GPIO6CFG */ +#define RSTB0899_GPIO6CFG 44 +#define FSTB0899_GPIO6_OPDRAIN 233 +#define FSTB0899_GPIO6_CONFIG 234 +#define FSTB0899_GPIO6_XOR 235 + +/* GPIO7CFG */ +#define RSTB0899_GPIO7CFG 45 +#define FSTB0899_GPIO7_OPDRAIN 236 +#define FSTB0899_GPIO7_CONFIG 237 +#define FSTB0899_GPIO7_XOR 238 + +/* GPIO8CFG */ +#define RSTB0899_GPIO8CFG 46 +#define FSTB0899_GPIO8_OPDRAIN 239 +#define FSTB0899_GPIO8_CONFIG 240 +#define FSTB0899_GPIO8_XOR 241 + +/* GPIO9CFG */ +#define RSTB0899_GPIO9CFG 47 +#define FSTB0899_GPIO9_OPDRAIN 242 +#define FSTB0899_GPIO9_CONFIG 243 +#define FSTB0899_GPIO9_XOR 244 + +/* GPIO10CFG */ +#define RSTB0899_GPIO10CFG 48 +#define FSTB0899_GPIO10_OPDRAIN 245 +#define FSTB0899_GPIO10_CONFIG 246 +#define FSTB0899_GPIO10_XOR 247 + +/* GPIO11CFG */ +#define RSTB0899_GPIO11CFG 49 +#define FSTB0899_GPIO11_OPDRAIN 248 +#define FSTB0899_GPIO11_CONFIG 249 +#define FSTB0899_GPIO11_XOR 250 + +/* GPIO12CFG */ +#define RSTB0899_GPIO12CFG 50 +#define FSTB0899_GPIO12_OPDRAIN 251 +#define FSTB0899_GPIO12_CONFIG 252 +#define FSTB0899_GPIO12_XOR 253 + +/* GPIO13CFG */ +#define RSTB0899_GPIO13CFG 51 +#define FSTB0899_GPIO13_OPDRAIN 254 +#define FSTB0899_GPIO13_CONFIG 255 +#define FSTB0899_GPIO13_XOR 256 + +/* GPIO14CFG */ +#define RSTB0899_GPIO14CFG 52 +#define FSTB0899_GPIO14_OPDRAIN 257 +#define FSTB0899_GPIO14_CONFIG 258 +#define FSTB0899_GPIO14_XOR 259 + +/* GPIO15CFG */ +#define RSTB0899_GPIO15CFG 53 +#define FSTB0899_GPIO15_OPDRAIN 260 +#define FSTB0899_GPIO15_CONFIG 261 +#define FSTB0899_GPIO15_XOR 262 + +/* GPIO16CFG */ +#define RSTB0899_GPIO16CFG 54 +#define FSTB0899_GPIO16_OPDRAIN 263 +#define FSTB0899_GPIO16_CONFIG 264 +#define FSTB0899_GPIO16_XOR 265 + +/* GPIO17CFG */ +#define RSTB0899_GPIO17CFG 55 +#define FSTB0899_GPIO17_OPDRAIN 266 +#define FSTB0899_GPIO17_CONFIG 267 +#define FSTB0899_GPIO17_XOR 268 + +/* GPIO18CFG */ +#define RSTB0899_GPIO18CFG 56 +#define FSTB0899_GPIO18_OPDRAIN 269 +#define FSTB0899_GPIO18_CONFIG 270 +#define FSTB0899_GPIO18_XOR 271 + +/* GPIO19CFG */ +#define RSTB0899_GPIO19CFG 57 +#define FSTB0899_GPIO19_OPDRAIN 272 +#define FSTB0899_GPIO19_CONFIG 273 +#define FSTB0899_GPIO19_XOR 274 + +/* GPIO20CFG */ +#define RSTB0899_GPIO20CFG 58 +#define FSTB0899_GPIO20_OPDRAIN 275 +#define FSTB0899_GPIO20_CONFIG 276 +#define FSTB0899_GPIO20_XOR 277 + +/* SDATCFG */ +#define RSTB0899_SDATCFG 59 +#define FSTB0899_SDAT_OPDRAIN 278 +#define FSTB0899_SDAT_CONFIG 279 +#define FSTB0899_SDAT_XOR 280 + +/* SCLTCFG */ +#define RSTB0899_SCLTCFG 60 +#define FSTB0899_SCLT_OPDRAIN 281 +#define FSTB0899_SCLT_CONFIG 282 +#define FSTB0899_SCLT_XOR 283 + +/* AGCRFCFG */ +#define RSTB0899_AGCRFCFG 61 +#define FSTB0899_AGCRF_OPDRAIN 284 +#define FSTB0899_AGCRF_CONFIG 285 +#define FSTB0899_AGCRF_XOR 286 + +/* AGCBB2CFG */ +#define RSTB0899_AGCBB2CFG 62 +#define FSTB0899_AGCBB2_OPDRAIN 287 +#define FSTB0899_AGCBB2_CONFIG 288 +#define FSTB0899_AGCBB2_XOR 289 + +/* AGCBB1CFG */ +#define RSTB0899_AGCBB1CFG 63 +#define FSTB0899_AGCBB1_OPDRAIN 290 +#define FSTB0899_AGCBB1_CONFIG 291 +#define FSTB0899_AGCBB1_XOR 292 + +/* DIRCLKCFG */ +#define RSTB0899_DIRCLKCFG 64 +#define FSTB0899_DIRCLK_OPDRAIN 293 +#define FSTB0899_DIRCLK_CONFIG 294 +#define FSTB0899_DIRCLK_XOR 295 + +/* CKOUT27CFG */ +#define RSTB0899_CKOUT27CFG 65 +#define FSTB0899_CKOUT27_OPDRAIN 296 +#define FSTB0899_CKOUT27_CONFIG 297 +#define FSTB0899_CKOUT27_XOR 298 + +/* STDBYCFG */ +#define RSTB0899_STDBYCFG 66 +#define FSTB0899_STDBY_OPDRAIN 299 +#define FSTB0899_STDBY_CONFIG 300 +#define FSTB0899_STDBY_XOR 301 + +/* CS0CFG */ +#define RSTB0899_CS0CFG 67 +#define FSTB0899_CS0_OPDRAIN 302 +#define FSTB0899_CS0_CONFIG 303 +#define FSTB0899_CS0_XOR 304 + +/* CS1CFG */ +#define RSTB0899_CS1CFG 68 +#define FSTB0899_CS1_OPDRAIN 305 +#define FSTB0899_CS1_CONFIG 306 +#define FSTB0899_CS1_XOR 307 + +/* DISEQCOCFG */ +#define RSTB0899_DISEQCOCFG 69 +#define FSTB0899_DISEQCO_OPDRAIN 308 +#define FSTB0899_DISEQCO_CONFIG 309 +#define FSTB0899_DISEQCO_XOR 310 + +/* GPIO32CFG */ +#define RSTB0899_GPIO32CFG 70 +#define FSTB0899_GPIO32_OPDRAIN 311 +#define FSTB0899_GPIO32_CONFIG 312 +#define FSTB0899_GPIO32_XOR 313 + +/* GPIO33CFG */ +#define RSTB0899_GPIO33CFG 71 +#define FSTB0899_GPIO33_OPDRAIN 314 +#define FSTB0899_GPIO33_CONFIG 315 +#define FSTB0899_GPIO33_XOR 316 + +/* GPIO34CFG */ +#define RSTB0899_GPIO34CFG 72 +#define FSTB0899_GPIO34_OPDRAIN 317 +#define FSTB0899_GPIO34_CONFIG 318 +#define FSTB0899_GPIO34_XOR 319 + +/* GPIO35CFG */ +#define RSTB0899_GPIO35CFG 73 +#define FSTB0899_GPIO35_OPDRAIN 320 +#define FSTB0899_GPIO35_CONFIG 321 +#define FSTB0899_GPIO35_XOR 322 + +/* GPIO36CFG */ +#define RSTB0899_GPIO36CFG 74 +#define FSTB0899_GPIO36_OPDRAIN 323 +#define FSTB0899_GPIO36_CONFIG 324 +#define FSTB0899_GPIO36_XOR 325 + +/* GPIO37CFG */ +#define RSTB0899_GPIO37CFG 75 +#define FSTB0899_GPIO37_OPDRAIN 326 +#define FSTB0899_GPIO37_CONFIG 327 +#define FSTB0899_GPIO37_XOR 328 + +/* GPIO38CFG */ +#define RSTB0899_GPIO38CFG 76 +#define FSTB0899_GPIO38_OPDRAIN 329 +#define FSTB0899_GPIO38_CONFIG 330 +#define FSTB0899_GPIO38_XOR 331 + +/* GPIO39CFG */ +#define RSTB0899_GPIO39CFG 77 +#define FSTB0899_GPIO39_OPDRAIN 332 +#define FSTB0899_GPIO39_CONFIG 333 +#define FSTB0899_GPIO39_XOR 334 + +/* NCOARSE */ +#define RSTB0899_NCOARSE 78 +#define FSTB0899_MDIV 335 + +/* SYNTCTRL */ +#define RSTB0899_SYNTCTRL 79 +#define FSTB0899_STANDBY 336 +#define FSTB0899_BYPASS_PLLCORE 337 +#define FSTB0899_SELX1RATIO 338 +#define FSTB0899_I2C_TUD 339 +#define FSTB0899_STOP_PLL 340 +#define FSTB0899_SYNTCTRL_RESERVED 341 +#define FSTB0899_SELOSCI 342 +#define FSTB0899_BYPASSPLLADC 343 + +/* FILTCTRL */ +#define RSTB0899_FILTCTRL 80 +#define FSTB0899_INVCLK90 344 +#define FSTB0899_PERMBYPDIS 345 +#define FSTB0899_CLKSWITCH 346 +#define FSTB0899_FILTCTRL_RESERVED 347 + +/* SYSCTRL */ +#define RSTB0899_SYSCTRL 81 +#define FSTB0899_SYSCTRL_RESERVED 348 +#define FSTB0899_PLLLOCKED 349 + +/* STOPCLK1 */ +#define RSTB0899_STOPCLK1 82 +#define FSTB0899_STOP_CKINTBUF90 350 +#define FSTB0899_STOP_CKINTBUF180 351 +#define FSTB0899_STOP_CKH8PSK90 352 +#define FSTB0899_STOP_CKFEC90 353 +#define FSTB0899_STOP_CKFEC180 354 +#define FSTB0899_STOP_CKCORE270 355 +#define FSTB0899_STOP_CKADCI90 356 +#define FSTB0899_STOP_INVCKADCI90 357 + +/* STOPCLK2 */ +#define RSTB0899_STOPCLK2 83 +#define FSTB0899_STOPCLK2_RESERVED 358 +#define FSTB0899_STOP_CKS2DMD90 359 +#define FSTB0899_STOP_CKPKDLIN90 360 +#define FSTB0899_STOP_CKPKDLIN180 361 + +/* TSTTNR1 */ +#define RSTB0899_TSTTNR1 84 +#define FSTB0899_BYPASS_ADC 362 +#define FSTB0899_INVADCICKOUT 363 +#define FSTB0899_ADCTEST_VOLTAGE 364 +#define FSTB0899_ADC_RESET 365 +#define FSTB0899_TSTTNR1_2 366 +#define FSTB0899_ADCPON 367 +#define FSTB0899_ADCIN_MODE 368 + +/* TSTTNR2 */ +#define RSTB0899_TSTTNR2 85 +#define FSTB0899_TSTTNR2_7 369 +#define FSTB0899_NOT_DISRX_WIRED 370 +#define FSTB0899_DISEQC_DCURRENT 371 +#define FSTB0899_DISEQC_ZCURRENT 372 +#define FSTB0899_DISEQC_SINC_SOURCE 373 +#define FSTB0899_SELIQSRC 374 + +/* TSTTNR3 */ +#define RSTB0899_TSTTNR3 86 +#define FSTB0899_TSTTNR3_7 375 +#define FSTB0899_TSTTNR3_6 376 +#define FSTB0899_TSTTNR3_5 377 +#define FSTB0899_TSTTNR3_4 378 +#define FSTB0899_TSTTNR3_3 379 +#define FSTB0899_TSTTNR3_2 380 +#define FSTB0899_TSTTNR3_1 381 +#define FSTB0899_TSTTNR3_0 382 + +/* INTBUFSTATUS */ +#define RSTB0899_INTBUFSTATUS 87 +#define FSTB0899_INTBUF_FIFO_FULL 383 + +/* INTBUFCTRL */ +#define RSTB0899_INTBUFCTRL 88 +#define FSTB0899_H8S2_PATH_DECODE 384 +#define FSTB0899_FIFO_ENABLE 385 +#define FSTB0899_INTBUF_SOFTRESET 386 + +/* DMDSTATUS */ +#define RSTB0899_DMDSTATUS 89 +#define FSTB0899_IF_AGCLOCK 387 + +/* CRLFREQ */ +#define RSTB0899_CRLFREQ 90 +#define FSTB0899_CRL_FREQUENCY 388 + +/* BTRFREQ */ +#define RSTB0899_BTRFREQ 91 +#define FSTB0899_BTR_FREQUENCY 389 + +/* IFAGCGAIN */ +#define RSTB0899_IFAGCGAIN 92 +#define FSTB0899_IF_AGCGAIN 390 + +/* BBAGCGAIN */ +#define RSTB0899_BBAGCGAIN 93 +#define FSTB0899_BB_AGCGAIN 391 + +/* DCOFFSET */ +#define RSTB0899_DCOFFSET 94 +#define FSTB0899_I_DCOFFSET 392 +#define FSTB0899_Q_DCOFFSET 393 + +/* DMDCNTRL */ +#define RSTB0899_DMDCNTRL 95 +#define FSTB0899_ADC0_PINS1IN 394 +#define FSTB0899_IN2COMP1_OFFBIN0 395 +#define FSTB0899_DC_COMP 396 +#define FSTB0899_MODMODE 397 + +/* IFAGCCNTRL */ +#define RSTB0899_IFAGCCNTRL 96 +#define FSTB0899_IF_GAININIT 398 +#define FSTB0899_IF_AGCSENSE 399 +#define FSTB0899_IF_LOOPGAIN 400 +#define FSTB0899_IF_LDGAININIT 401 +#define FSTB0899_IF_AGCREF 402 + +/* BBAGCCNTRL */ +#define RSTB0899_BBAGCCNTRL 97 +#define FSTB0899_BBGAIN_INIT 403 +#define FSTB0899_BBLOOP_GAIN 404 +#define FSTB0899_BBLDGAIN_INIT 405 +#define FSTB0899_BB_AGCREF 406 + +/* CRLCNTRL */ +#define RSTB0899_CRLCNTRL 98 +#define FSTB0899_CRL_LOCK_CLEAR 407 +#define FSTB0899_CRL_CLR_SWEEPER 408 +#define FSTB0899_CRL_SWEEP_EN 409 +#define FSTB0899_CRL_DETECTOR_SEL 410 +#define FSTB0899_CRL_SENSE 411 +#define FSTB0899_CRL_CLR_PHSERR 412 + +/* CRLPHSINIT */ +#define RSTB0899_CRLPHSINIT 99 +#define FSTB0899_CRLPHSINIT31 413 +#define FSTB0899_CRL_LD_INIT_PHASE 414 +#define FSTB0899_CRL_INIT_PHASE 415 + +/* CRLFREQINIT */ +#define RSTB0899_CRLFREQINIT 100 +#define FSTB0899_CRLFREQINIT31 416 +#define FSTB0899_CRL_LD_FREQ_INIT 417 +#define FSTB0899_CRL_FREQ_INIT 418 + +/* CRLLOOPGAIN */ +#define RSTB0899_CRLLOOPGAIN 101 +#define FSTB0899_KCRL2_RSHFT 419 +#define FSTB0899_KCRL1 420 +#define FSTB0899_KCRL1_RSHFT 421 +#define FSTB0899_KCRL0 422 +#define FSTB0899_KCRL0_RSHFT 423 + +/* CRLNOMFREQ */ +#define RSTB0899_CRLNOMFREQ 102 +#define FSTB0899_CRLNOM_FREQ 424 + +/* CRLSWPRATE */ +#define RSTB0899_CRLSWPRATE 103 +#define FSTB0899_CRL_SWP_RATE 425 + +/* CRLMAXSWP */ +#define RSTB0899_CRLMAXSWP 104 +#define FSTB0899_CRL_MAX_SWP 426 + +/* CRLLKCNTRL */ +#define RSTB0899_CRLLKCNTRL 105 +#define FSTB0899_CRL_PWR_DET 427 +#define FSTB0899_THRESHOLD_LI 428 +#define FSTB0899_THRESHOLD_HI 429 +#define FSTB0899_CRLK_GAIN 430 +#define FSTB0899_CRLK_FC 431 + +/* DECIMCNTRL */ +#define RSTB0899_DECIMCNTRL 106 +#define FSTB0899_BANDLIMIT_B 432 +#define FSTB0899_WIN_SEL 433 +#define FSTB0899_DECIM_RATE 434 + +/* BTRCNTRL */ +#define RSTB0899_BTRCNTRL 107 +#define FSTB0899_BTRFREQ_CORR 435 +#define FSTB0899_BTRCLR_LOCK 436 +#define FSTB0899_BTR_SENS 437 +#define FSTB0899_BTRERR_ENA 438 +#define FSTB0899_INTRP_PHS_SENS 439 + +/* BTRLOOPGAIN */ +#define RSTB0899_BTRLOOPGAIN 108 +#define FSTB0899_KBTR2_RSHT 440 +#define FSTB0899_KBTR1 441 +#define FSTB0899_KBTR1_RSHT 442 +#define FSTB0899_KBTR0 443 +#define FSTB0899_KBTR0_RSHFT 444 + +/* BTRPHSINIT */ +#define RSTB0899_BTRPHSINIT 109 +#define FSTB0899_BTRID_PHASEINIT 445 +#define FSTB0899_BTR_INITPHASE 446 + +/* BTRFREQINIT */ +#define RSTB0899_BTRFREQINIT 110 +#define FSTB0899_BTRID_FREQINIT 447 +#define FSTB0899_BTR_FREQINIT 448 + +/* BTRNOMFREQ */ +#define RSTB0899_BTRNOMFREQ 111 +#define FSTB0899_BTRNOM_FREQ 449 + +/* BTRLKCNTRL */ +#define RSTB0899_BTRLKCNTRL 112 +#define FSTB0899_BTR_MINENERGY 450 +#define FSTB0899_BTR_LOCK_THRESHOLDLO 451 +#define FSTB0899_BTR_LOCK_THRESHOLDHI 452 +#define FSTB0899_BTR_LOCKGAIN 453 +#define FSTB0899_BTR_LOCK_LEAKFACTOR 454 + +/* DECNCNTRL */ +#define RSTB0899_DECNCNTRL 113 +#define FSTB0899_INVERT_Q 455 +#define FSTB0899_INVERT_I 456 +#define FSTB0899_SWAP_IQ 457 +#define FSTB0899_SOFT_THRESHOLD 458 + +/* TPCNTRL */ +#define RSTB0899_TPCNTRL 114 +#define FSTB0899_TP_MSB1LSB0_SEL 459 +#define FSTB0899_CAPTURE 460 +#define FSTB0899_TP_BLK_SEL 461 +#define FSTB0899_TP_SIG_SEL 462 +#define FSTB0899_TP_SEL 463 + +/* TPBUFSTATUS */ +#define RSTB0899_TPBUFSTATUS 115 +#define FSTB0899_BUFFER_FULL 464 + +/* DCESTIM */ +#define RSTB0899_DCESTIM 116 +#define FSTB0899_I_DC_ESTIMATE 465 +#define FSTB0899_Q_DC_ESTIMATE 466 + +/* FLLCNTRL */ +#define RSTB0899_FLLCNTRL 117 +#define FSTB0899_CRL_FLL_ACC 467 +#define FSTB0899_FLL_AVG_PERIOD 468 + +/* FLLFREQWD */ +#define RSTB0899_FLLFREQWD 118 +#define FSTB0899_FLL_FREQ_WD 469 + +/* ANTIALIASSEL */ +#define RSTB0899_ANTIALIASSEL 119 +#define FSTB0899_ANTI_ALIAS_SEL 470 + +/* RRCALPHA */ +#define RSTB0899_RRCALPHA 120 +#define FSTB0899_RRC_ALPHA 471 + +/* DCADAPTISHFT */ +#define RSTB0899_DCADAPTISHFT 121 +#define FSTB0899_DC_ADAPT_ISHFT 472 + +/* IMBOFFSET */ +#define RSTB0899_IMBOFFSET 122 +#define FSTB0899_PHS_IMB_COMP 473 +#define FSTB0899_AMPL_IMB_COMP 474 + +/* IMBESTIMATE */ +#define RSTB0899_IMBESTIMATE 123 +#define FSTB0899_PHS_IMB_ESTIMATE 475 +#define FSTB0899_AMPL_IMB_ESTIMATE 476 + +/* IMBCNTRL */ +#define RSTB0899_IMBCNTRL 124 +#define FSTB0899_PHS_ADAPT_ISHFT 477 +#define FSTB0899_AMPL_ADAPT_ISHFT 478 +#define FSTB0899_IMB_COMP 479 + +/* IFAGCCNTRL2 */ +#define RSTB0899_IFAGCCNTRL2 125 +#define FSTB0899_IF_AGCLOCK_THRESH 480 +#define FSTB0899_IF_AGC_SDDIV 481 +#define FSTB0899_IF_AGC_DUMPPER 482 + +/* DMDCNTRL2 */ +#define RSTB0899_DMDCNTRL2 126 +#define FSTB0899_SPECTRUM_INVERT 483 +#define FSTB0899_AGC_MODE 484 +#define FSTB0899_CRL_FREQ_ADJ 485 + +/* TPBUFFER */ +#define RSTB0899_TPBUFFER 127 +#define FSTB0899_TP_BUFFER_IN 486 + +/* TPBUFFER1 */ +#define RSTB0899_TPBUFFER1 128 +#define FSTB0899_TP_BUFFER_IN1 487 + +/* TPBUFFER2 */ +#define RSTB0899_TPBUFFER2 129 +#define FSTB0899_TP_BUFFER_IN2 488 + +/* TPBUFFER3 */ +#define RSTB0899_TPBUFFER3 130 +#define FSTB0899_TP_BUFFER_IN3 489 + +/* TPBUFFER4 */ +#define RSTB0899_TPBUFFER4 131 +#define FSTB0899_TP_BUFFER_IN4 490 + +/* TPBUFFER5 */ +#define RSTB0899_TPBUFFER5 132 +#define FSTB0899_TP_BUFFER_IN5 491 + +/* TPBUFFER6 */ +#define RSTB0899_TPBUFFER6 133 +#define FSTB0899_TP_BUFFER_IN6 492 + +/* TPBUFFER7 */ +#define RSTB0899_TPBUFFER7 134 +#define FSTB0899_TP_BUFFER_IN7 493 + +/* TPBUFFER8 */ +#define RSTB0899_TPBUFFER8 135 +#define FSTB0899_TP_BUFFER_IN8 494 + +/* TPBUFFER9 */ +#define RSTB0899_TPBUFFER9 136 +#define FSTB0899_TP_BUFFER_IN9 495 + +/* TPBUFFER10 */ +#define RSTB0899_TPBUFFER10 137 +#define FSTB0899_TP_BUFFER_IN10 496 + +/* TPBUFFER11 */ +#define RSTB0899_TPBUFFER11 138 +#define FSTB0899_TP_BUFFER_IN11 497 + +/* TPBUFFER12 */ +#define RSTB0899_TPBUFFER12 139 +#define FSTB0899_TP_BUFFER_IN12 498 + +/* TPBUFFER13 */ +#define RSTB0899_TPBUFFER13 140 +#define FSTB0899_TP_BUFFER_IN13 499 + +/* TPBUFFER14 */ +#define RSTB0899_TPBUFFER14 141 +#define FSTB0899_TP_BUFFER_IN14 500 + +/* TPBUFFER15 */ +#define RSTB0899_TPBUFFER15 142 +#define FSTB0899_TP_BUFFER_IN15 501 + +/* TPBUFFER16 */ +#define RSTB0899_TPBUFFER16 143 +#define FSTB0899_TP_BUFFER_IN16 502 + +/* TPBUFFER17 */ +#define RSTB0899_TPBUFFER17 144 +#define FSTB0899_TP_BUFFER_IN17 503 + +/* TPBUFFER18 */ +#define RSTB0899_TPBUFFER18 145 +#define FSTB0899_TP_BUFFER_IN18 504 + +/* TPBUFFER19 */ +#define RSTB0899_TPBUFFER19 146 +#define FSTB0899_TP_BUFFER_IN19 505 + +/* TPBUFFER20 */ +#define RSTB0899_TPBUFFER20 147 +#define FSTB0899_TP_BUFFER_IN20 506 + +/* TPBUFFER21 */ +#define RSTB0899_TPBUFFER21 148 +#define FSTB0899_TP_BUFFER_IN21 507 + +/* TPBUFFER22 */ +#define RSTB0899_TPBUFFER22 149 +#define FSTB0899_TP_BUFFER_IN22 508 + +/* TPBUFFER23 */ +#define RSTB0899_TPBUFFER23 150 +#define FSTB0899_TP_BUFFER_IN23 509 + +/* TPBUFFER24 */ +#define RSTB0899_TPBUFFER24 151 +#define FSTB0899_TP_BUFFER_IN24 510 + +/* TPBUFFER25 */ +#define RSTB0899_TPBUFFER25 152 +#define FSTB0899_TP_BUFFER_IN25 511 + +/* TPBUFFER26 */ +#define RSTB0899_TPBUFFER26 153 +#define FSTB0899_TP_BUFFER_IN26 512 + +/* TPBUFFER27 */ +#define RSTB0899_TPBUFFER27 154 +#define FSTB0899_TP_BUFFER_IN27 513 + +/* TPBUFFER28 */ +#define RSTB0899_TPBUFFER28 155 +#define FSTB0899_TP_BUFFER_IN28 514 + +/* TPBUFFER29 */ +#define RSTB0899_TPBUFFER29 156 +#define FSTB0899_TP_BUFFER_IN29 515 + +/* TPBUFFER30 */ +#define RSTB0899_TPBUFFER30 157 +#define FSTB0899_TP_BUFFER_IN30 516 + +/* TPBUFFER31 */ +#define RSTB0899_TPBUFFER31 158 +#define FSTB0899_TP_BUFFER_IN31 517 + +/* TPBUFFER32 */ +#define RSTB0899_TPBUFFER32 159 +#define FSTB0899_TP_BUFFER_IN32 518 + +/* TPBUFFER33 */ +#define RSTB0899_TPBUFFER33 160 +#define FSTB0899_TP_BUFFER_IN33 519 + +/* TPBUFFER34 */ +#define RSTB0899_TPBUFFER34 161 +#define FSTB0899_TP_BUFFER_IN34 520 + +/* TPBUFFER35 */ +#define RSTB0899_TPBUFFER35 162 +#define FSTB0899_TP_BUFFER_IN35 521 + +/* TPBUFFER36 */ +#define RSTB0899_TPBUFFER36 163 +#define FSTB0899_TP_BUFFER_IN36 522 + +/* TPBUFFER37 */ +#define RSTB0899_TPBUFFER37 164 +#define FSTB0899_TP_BUFFER_IN37 523 + +/* TPBUFFER38 */ +#define RSTB0899_TPBUFFER38 165 +#define FSTB0899_TP_BUFFER_IN38 524 + +/* TPBUFFER39 */ +#define RSTB0899_TPBUFFER39 166 +#define FSTB0899_TP_BUFFER_IN39 525 + +/* TPBUFFER40 */ +#define RSTB0899_TPBUFFER40 167 +#define FSTB0899_TP_BUFFER_IN40 526 + +/* TPBUFFER41 */ +#define RSTB0899_TPBUFFER41 168 +#define FSTB0899_TP_BUFFER_IN41 527 + +/* TPBUFFER42 */ +#define RSTB0899_TPBUFFER42 169 +#define FSTB0899_TP_BUFFER_IN42 528 + +/* TPBUFFER43 */ +#define RSTB0899_TPBUFFER43 170 +#define FSTB0899_TP_BUFFER_IN43 529 + +/* TPBUFFER44 */ +#define RSTB0899_TPBUFFER44 171 +#define FSTB0899_TP_BUFFER_IN44 530 + +/* TPBUFFER45 */ +#define RSTB0899_TPBUFFER45 172 +#define FSTB0899_TP_BUFFER_IN45 531 + +/* TPBUFFER46 */ +#define RSTB0899_TPBUFFER46 173 +#define FSTB0899_TP_BUFFER_IN46 532 + +/* TPBUFFER47 */ +#define RSTB0899_TPBUFFER47 174 +#define FSTB0899_TP_BUFFER_IN47 533 + +/* TPBUFFER48 */ +#define RSTB0899_TPBUFFER48 175 +#define FSTB0899_TP_BUFFER_IN48 534 + +/* TPBUFFER49 */ +#define RSTB0899_TPBUFFER49 176 +#define FSTB0899_TP_BUFFER_IN49 535 + +/* TPBUFFER50 */ +#define RSTB0899_TPBUFFER50 177 +#define FSTB0899_TP_BUFFER_IN50 536 + +/* TPBUFFER51 */ +#define RSTB0899_TPBUFFER51 178 +#define FSTB0899_TP_BUFFER_IN51 537 + +/* TPBUFFER52 */ +#define RSTB0899_TPBUFFER52 179 +#define FSTB0899_TP_BUFFER_IN52 538 + +/* TPBUFFER53 */ +#define RSTB0899_TPBUFFER53 180 +#define FSTB0899_TP_BUFFER_IN53 539 + +/* TPBUFFER54 */ +#define RSTB0899_TPBUFFER54 181 +#define FSTB0899_TP_BUFFER_IN54 540 + +/* TPBUFFER55 */ +#define RSTB0899_TPBUFFER55 182 +#define FSTB0899_TP_BUFFER_IN55 541 + +/* TPBUFFER56 */ +#define RSTB0899_TPBUFFER56 183 +#define FSTB0899_TP_BUFFER_IN56 542 + +/* TPBUFFER57 */ +#define RSTB0899_TPBUFFER57 184 +#define FSTB0899_TP_BUFFER_IN57 543 + +/* TPBUFFER58 */ +#define RSTB0899_TPBUFFER58 185 +#define FSTB0899_TP_BUFFER_IN58 544 + +/* TPBUFFER59 */ +#define RSTB0899_TPBUFFER59 186 +#define FSTB0899_TP_BUFFER_IN59 545 + +/* TPBUFFER60 */ +#define RSTB0899_TPBUFFER60 187 +#define FSTB0899_TP_BUFFER_IN60 546 + +/* TPBUFFER61 */ +#define RSTB0899_TPBUFFER61 188 +#define FSTB0899_TP_BUFFER_IN61 547 + +/* TPBUFFER62 */ +#define RSTB0899_TPBUFFER62 189 +#define FSTB0899_TP_BUFFER_IN62 548 + +/* TPBUFFER63 */ +#define RSTB0899_TPBUFFER63 190 +#define FSTB0899_TP_BUFFER_IN63 549 + +/* RESETCNTRL */ +#define RSTB0899_RESETCNTRL 191 +#define FSTB0899_DVBS2_SRST 550 + +/* ACMENABLE */ +#define RSTB0899_ACMENABLE 192 +#define FSTB0899_ACM_ENABLE 551 + +/* DESCRCNTRL */ +#define RSTB0899_DESCRCNTRL 193 +#define FSTB0899_DESCR_CNTRL 552 + +/* CSMCNTRL1 */ +#define RSTB0899_CSMCNTRL1 194 +#define FSTB0899_FORCE_FREQLOCK_STATE 553 +#define FSTB0899_FREQLOCK_STATE 554 +#define FSTB0899_AUTO_PARAM 555 +#define FSTB0899_FE_LOOP_SHIFT 556 +#define FSTB0899_CSM_AGC_SHIFT 557 +#define FSTB0899_CSM_AGC_GAIN 558 +#define FSTB0899_CSM_TOW_PASS 559 +#define FSTB0899_CSM_DVT_TABLE 560 + +/* CSMCNTRL2 */ +#define RSTB0899_CSMCNTRL2 195 +#define FSTB0899_CSM_GAMMA_RHOACQ 561 +#define FSTB0899_CSM_GAMMA_ACQ 562 + +/* CSMCNTRL3 */ +#define RSTB0899_CSMCNTRL3 196 +#define FSTB0899_CSM_GAMMA_RHOTRACK 563 +#define FSTB0899_CSM_GAMMA_TRACK 564 + +/* CSMCNTRL4 */ +#define RSTB0899_CSMCNTRL4 197 +#define FSTB0899_PHASE_DIFF_THRESHOLD 565 +#define FSTB0899_LOCK_COUNT_THRESHOLD 566 + +/* UWPCNTRL1 */ +#define RSTB0899_UWPCNTRL1 198 +#define FSTB0899_UWP_THRESHOLD_SOF 567 +#define FSTB0899_UWP_ESN0_QUANT 568 +#define FSTB0899_UWP_ESN0_AVE 569 +#define FSTB0899_UWP_START 570 + +/* UWPCNTRL2 */ +#define RSTB0899_UWPCNTRL2 199 +#define FSTB0899_UWP_MISS_THRESHOLD 571 +#define FSTB0899_FE_FINE_TRK 572 +#define FSTB0899_FE_COARSE_TRK 573 + +/* UWPSTAT1 */ +#define RSTB0899_UWPSTAT1 200 +#define FSTB0899_UWP_STATE 574 +#define FSTB0899_UW_MAX_PEAK 575 + +/* UWPSTAT2 */ +#define RSTB0899_UWPSTAT2 201 +#define FSTB0899_ESN0_ESR 576 +#define FSTB0899_UWP_DECODED_MODCODE 577 + +/* DMDSTAT2 */ +#define RSTB0899_DMDSTAT2 202 +#define FSTB0899_CSM_LOCK 578 +#define FSTB0899_UWP_LOCK 579 + +/* FREQADJSCALE */ +#define RSTB0899_FREQADJSCALE 203 +#define FSTB0899_FREQ_ADJ_SCALE 580 + +/* UWPCNTRL3 */ +#define RSTB0899_UWPCNTRL3 204 +#define FSTB0899_UWP_THRESHOLD_TRACK 581 +#define FSTB0899_UWP_THRESHOLD_ACQ 582 + +/* SYMCLKSEL */ +#define RSTB0899_SYMCLKSEL 205 +#define FSTB0899_SYM_CLK_SEL 583 + +/* SOFSRCHTO */ +#define RSTB0899_SOFSRCHTO 206 +#define FSTB0899_SOF_SEARCH_TIMEOUT 584 + +/* ACQCNTRL1 */ +#define RSTB0899_ACQCNTRL1 207 +#define FSTB0899_FE_FINE_ACQ 585 +#define FSTB0899_FE_CORASE_ACQ 586 + +/* ACQCNTRL2 */ +#define RSTB0899_ACQCNTRL2 208 +#define FSTB0899_ZIGZAG 587 +#define FSTB0899_NUM_STEPS 588 +#define FSTB0899_FREQ_STEP_SIZE 589 + +/* ACQCNTRL3 */ +#define RSTB0899_ACQCNTRL3 209 +#define FSTB0899_THRESHOLD_SCL 590 +#define FSTB0899_UWP_THRESHOLD_SRCH 591 +#define FSTB0899_AUTO_REACQUIRE 592 +#define FSTB0899_TRACK_LOCK_SEL 593 +#define FSTB0899_ACQ_SEARCH_MODE 594 +#define FSTB0899_CONFIRM_FRAMES 595 + +/* FESETTLE */ +#define RSTB0899_FESETTLE 210 +#define FSTB0899_SETTING_TIME 596 + +/* ACDWELL */ +#define RSTB0899_ACDWELL 211 +#define FSTB0899_DWELL_TIME 597 + +/* ACQUIRETRIG */ +#define RSTB0899_ACQUIRETRIG 212 +#define FSTB0899_ACQUIRE 598 + +/* LOCKLOST */ +#define RSTB0899_LOCKLOST 213 +#define FSTB0899_LOCK_LOST 599 + +/* ACQSTAT1 */ +#define RSTB0899_ACQSTAT1 214 +#define FSTB0899_STEP_FREQ 600 +#define FSTB0899_ACQ_STATE 601 +#define FSTB0899_UW_DETECT_COUNT 602 + +/* ACQTIMEOUT */ +#define RSTB0899_ACQTIMEOUT 215 +#define FSTB0899_ACQ_TIMEOUT 603 + +/* ACQTIME */ +#define RSTB0899_ACQTIME 216 +#define FSTB0899_ACQ_TIME_SYM 604 + +/* FINALAGCCNTRL */ +#define RSTB0899_FINALAGCCNTRL 217 +#define FSTB0899_FINAL_GAIN_INIT 605 +#define FSTB0899_FINAL_LOOP_GAIN 606 +#define FSTB0899_FINAL_LDGAIN_INIT 607 +#define FSTB0899_FINAL_AGC_REF 608 + +/* FINALAGCCGAIN */ +#define RSTB0899_FINALAGCCGAIN 218 +#define FSTB0899_FINAL_AGC_GAIN 609 + +/* EQUILIZERINIT */ +#define RSTB0899_EQUILIZERINIT 219 +#define FSTB0899_EQ_SRST 610 +#define FSTB0899_EQ_INIT 611 + +/* EQCNTL */ +#define RSTB0899_EQCNTL 220 +#define FSTB0899_EQ_ADAPT_MODE 612 +#define FSTB0899_EQ_DELAY 613 +#define FSTB0899_EQ_QUANT_LEVEL 614 +#define FSTB0899_EQ_DISABLE_UPDATE 615 +#define FSTB0899_EQ_BYPASS 616 +#define FSTB0899_EQ_SHIFT 617 + +/* EQIINITCOEFF0 */ +#define RSTB0899_EQIINITCOEFF0 221 +#define FSTB0899_EQ_I_INITCOEFF0 618 + +/* EQIINITCOEFF1 */ +#define RSTB0899_EQIINITCOEFF1 222 +#define FSTB0899_EQ_I_INITCOEFF1 619 + +/* EQIINITCOEFF2 */ +#define RSTB0899_EQIINITCOEFF2 223 +#define FSTB0899_EQ_I_INITCOEFF2 620 + +/* EQIINITCOEFF3 */ +#define RSTB0899_EQIINITCOEFF3 224 +#define FSTB0899_EQ_I_INITCOEFF3 621 + +/* EQIINITCOEFF4 */ +#define RSTB0899_EQIINITCOEFF4 225 +#define FSTB0899_EQ_I_INITCOEFF4 622 + +/* EQIINITCOEFF5 */ +#define RSTB0899_EQIINITCOEFF5 226 +#define FSTB0899_EQ_I_INITCOEFF5 623 + +/* EQIINITCOEFF6 */ +#define RSTB0899_EQIINITCOEFF6 227 +#define FSTB0899_EQ_I_INITCOEFF6 624 + +/* EQIINITCOEFF7 */ +#define RSTB0899_EQIINITCOEFF7 228 +#define FSTB0899_EQ_I_INITCOEFF7 625 + +/* EQIINITCOEFF8 */ +#define RSTB0899_EQIINITCOEFF8 229 +#define FSTB0899_EQ_I_INITCOEFF8 626 + +/* EQIINITCOEFF9 */ +#define RSTB0899_EQIINITCOEFF9 230 +#define FSTB0899_EQ_I_INITCOEFF9 627 + +/* EQIINITCOEFF10 */ +#define RSTB0899_EQIINITCOEFF10 231 +#define FSTB0899_EQ_I_INITCOEFF10 628 + +/* EQQINITCOEFF0 */ +#define RSTB0899_EQQINITCOEFF0 232 +#define FSTB0899_EQ_Q_INITCOEFF0 629 + +/* EQQINITCOEFF1 */ +#define RSTB0899_EQQINITCOEFF1 233 +#define FSTB0899_EQ_Q_INITCOEFF1 630 + +/* EQQINITCOEFF2 */ +#define RSTB0899_EQQINITCOEFF2 234 +#define FSTB0899_EQ_Q_INITCOEFF2 631 + +/* EQQINITCOEFF3 */ +#define RSTB0899_EQQINITCOEFF3 235 +#define FSTB0899_EQ_Q_INITCOEFF3 632 + +/* EQQINITCOEFF4 */ +#define RSTB0899_EQQINITCOEFF4 236 +#define FSTB0899_EQ_Q_INITCOEFF4 633 + +/* EQQINITCOEFF5 */ +#define RSTB0899_EQQINITCOEFF5 237 +#define FSTB0899_EQ_Q_INITCOEFF5 634 + +/* EQQINITCOEFF6 */ +#define RSTB0899_EQQINITCOEFF6 238 +#define FSTB0899_EQ_Q_INITCOEFF6 635 + +/* EQQINITCOEFF7 */ +#define RSTB0899_EQQINITCOEFF7 239 +#define FSTB0899_EQ_Q_INITCOEFF7 636 + +/* EQQINITCOEFF8 */ +#define RSTB0899_EQQINITCOEFF8 240 +#define FSTB0899_EQ_Q_INITCOEFF8 637 + +/* EQQINITCOEFF9 */ +#define RSTB0899_EQQINITCOEFF9 241 +#define FSTB0899_EQ_Q_INITCOEFF9 638 + +/* EQQINITCOEFF10 */ +#define RSTB0899_EQQINITCOEFF10 242 +#define FSTB0899_EQ_Q_INITCOEFF10 639 + +/* EQICOEFFSOUT0 */ +#define RSTB0899_EQICOEFFSOUT0 243 +#define FSTB0899_EQ_I_COEFFOUT0 640 + +/* EQICOEFFSOUT1 */ +#define RSTB0899_EQICOEFFSOUT1 244 +#define FSTB0899_EQ_I_COEFFOUT1 641 + +/* EQICOEFFSOUT2 */ +#define RSTB0899_EQICOEFFSOUT2 245 +#define FSTB0899_EQ_I_COEFFOUT2 642 + +/* EQICOEFFSOUT3 */ +#define RSTB0899_EQICOEFFSOUT3 246 +#define FSTB0899_EQ_I_COEFFOUT3 643 + +/* EQICOEFFSOUT4 */ +#define RSTB0899_EQICOEFFSOUT4 247 +#define FSTB0899_EQ_I_COEFFOUT4 644 + +/* EQICOEFFSOUT5 */ +#define RSTB0899_EQICOEFFSOUT5 24